Hi,
in the introduction i find: "At SDR clock frequencies below the maximum operating frequency (420 MHz) of the Virtex-II Digital Clock Manager (DCM), implementing a single data rate design can be easily accomplished using standard design techniques. This application note describes a method of implementing an SDR interface at clock frequencies higher than the maximum operating frequency of the DCM, without exceeding the AC timing specifications of the Virtex-II devices."
but later on, on page 3, the input ref_clk is connected to a DCM. Why is that possible? I thought the frequency is higher than the max DCM input frequency?
regards, Benjamin