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Memec S3-1500 board + P160 comms 2

Hi,

Has anyone tried connecting the P160 Comms2 module to the Memec S3-1500 board? Using Base System Builder with Memc's XBD files, it assumes the module is on P160 Slot A (left hand side of the board).

However, when placed in this slot the P160 MAC phy_rx_d pin, defined as 3.3V LVCMOS, connects to FPGA pin AD13 which is on the same IO bank as most of the main board's DDR signals (2.5V SSTL) e.g.:

fpga_0_DDR_SDRAM_16M IO SSTL2_I 1.25 2.50 PAD327 AC13 fpga_0_P160_Ethernet I LVCMOS33 NR 3.30 PAD326 AD13

PAR refuses to continue, and rightly so.

I'm redoing my constraints to try the module in the other slot, hopefully that will not have such a conflict.

If anyone from Insight/Memec is listening, please let your engineering teams know - or is this a known issue?

Cheers,

John

Reply to
John Williams
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OK so it's even worse :(

ERROR:Place:348 - The IOB fpga_0_P160_Ethernet_MAC_PHY_rx_data_pin is locked to site AE16 in bank 4. This violates the SelectIO banking rules.

ERROR:Place:348 - The IOB fpga_0_P160_Ethernet_MAC_PHY_dv_pin is locked to site AF17 in bank 4. This violates the SelectIO banking rules.

ERROR:Place:348 - The IOB fpga_0_P160_Ethernet_MAC_PHY_tx_er_pin is locked to site AE17 in bank 4. This violates the SelectIO banking rules.

and so it goes. There are about 7 Comms module IOs that are unplaceable because of this. At least in the left slot there's only one impossible IO.

Overall, it seems that the P160 Comms2 module is unusable with the S3MB1500 board.

Any ideas on how I might get past this? I could fudge the IOSTD constraints to force it to map, but intermixing 2.5V FPGA pins with 3.3V signals seems like a bad idea.

Thanks,

John

Reply to
John Williams

Hmm, perhaps I should stop talking to myself so much.

Anyway, a very helpful Insight engineer has helped to resolve this one. It's just a case of changing the IOSTD constraint to LVCMOS25, and trusting the source termination resistors on the P160 module to sufficiently reduce the 3.3V driving voltages down to the IO's clamping/protection thresholds. This Xilinx answer says more:

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Cheers,

John

Reply to
John Williams

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