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LUT based virtex multiplier

Hi,

I wonder if someone could suggest an efficient LUT based signed multiplication algorithm for Virtex FPGAs.

I've implemented an unsigned multiplier using the "computed partial product multipiler" algorithm described at:

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Is there some modification that will allow this to perform signed multiplication?

Looking around google hasn't turned up much except a possible suggestion that a booth multiplier might be the way to go. Is this the right approach, and if so, does anyone know of a reference regarding mapping it to LUTs?

Thanks,

Andy.

Reply to
evilkidder
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"Efficiency" is to some degree relative. Are you looking for best LUT-based speed? Best area? It is an UTTER shame not to use the embedded multipliers in modern FPGAs.

What size (including sign) for each of the input values? You want full output width, yes? Integers, right?

Reply to
John_H

I am attempting to write a simple synthesizer for a HDL I have been working on so I guess I am looking for algorithms at both ends of the scale. To start with a reasonable trade-off between the two so I can get the initial implementation of the ground will be fine.

I will be using them based on some as yet undecided criteria. From what I've read it should be relatively easy to support, expect perhaps differences in "DSP" slices between architectures. I've yet to look into if a V4 will implement a mult18x18 primitive for example or if you need to use a dsp48.

Basically any size. I intend to provide specific implementations for very small sizes but to start with I'll live with a generic version.

Yes. Again there will probably be some scope for optimisation in this regard later on, but for now my languages multiplier primitive is M*N -

If you mean twos complement, then yes.

Thanks,

Andy.

Reply to
evilkidder

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