Hi newsgroup,
I have got problems using Signal Tap with the Altera USB Blaster download cable. Sometimes the data collected is correct, sometimes not, sometimes I get a jtag communication error.
When I use the Altera Byteblaster MV download cable, I don't get those incorrect data nor jtag communication errors in Signal Tap and everything works fine.
In Quartus timing analyzer there are no failed paths.
As suggested in a newsgroup, I have set all unused pins to "inputs tristated".
I use Quartus 4.2 SP1 on windows 2000 SP4. PC ist a 2,4GHz Fujitsu Siemens Amilo D. I tried a different USB cable and a different USB port.
The target hardware is our own board with a EP1C12F256C8, VCCIO is 3,3V. TMS and TDI have a 10k Pullup to VCCIO, TCK has a 10k pulldown to gnd. The jtag connector is less than 2 inches away from the cyclone and this part of the schematic is from the altera nios board.
It seems linke the problem has something todo with the faster timing on jtag when using the USB Blaster. Is it possible to adjust the jtag frequency?
When I look at the JTAG signal "TCK" with the scope, I have the following results:
1.: Using Byteblaster MV: The signal edges reach 3,3V and are looking good.2.: using USB Blaster: The signal edges reach 3,3V but they break down to about 2,5V. It looks like a sawtooth.
I hope someone can help me in this newsgroup. It would be nice if someone could look at the TCK signal with the scope on his USB Blaster running Signal Tap.
I didn't get an answer from altera mysupport within 1 week.
Best regards Markus