JTAG is a chip test standard originally by the Joint Test Action Group. Currently the corresponding standard is IEEE 1149.
TAP is Test Access Port in the standard. It is a state-machine device on a JTAG-enabled chip. The state machine enables the tester to control the test electronics with one clock, one control, one data in and one data out signal.
The TAP and associated data ports are designed so that several chips using the ports may be chained together, so that the chips are seen as a single test port to the test equipment.
Boundary scan is a test method where specially constructed shift register cells are placed between the chip innards and the corresponding I/O pins. The calls enable (under TAP control) to read and set the pin signals and the signals from the pins to and from the chip internals.
ICE is usually In-Circuit Emulator, a piece of hardware added to a processor chip to help debugging the hardware and software with the processor. Pretty often the registers in the ICE are controlled via the JTAG port (under TAP control).
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