JTAG TAP

Hi,

I am writing a bit of software to control a JTAG port, but I am having a bit of trouble getting it working.

Below are the steps my software is following to test out a JTAG connection. I think that there must be an error in there somewhere, but from my understanding of the JTAG TAP and the way JTAG works, I can't see a problem at the moment.

Can anyone comment on whether I am controlling the TAP correctly?

Thanks,

Paul.

(Note: for each clock cycle below, tms and tdo are set before the clk is set high)

(1) Make sure TAP is in reset: clk 1: tms = 1, tdo = 0 clk 2: tms = 1, tdo = 0 clk 3: tms = 1, tdo = 0 clk 4: tms = 1, tdo = 0 clk 5: tms = 1, tdo = 0

(2) Move TAP to Select-DR-Scan state clk 6: tms = 0, tdo = 0 clk 7: tms = 1, tdo = 0

(3) Move TAP to SHIFT-IR clk 8: tms = 1, tdo = 0 clk 9: tms = 0, tdo = 0 clk 10: tms = 0, tdo = 0

(4) Shift 3 to put into bypass mode then move TAP to Select-DR-Scan state (IR length is 2 bits): clk 11: tms = 0, tdo = 1 clk 12: tms = 1, tdo = 1 clk 13: tms = 1, tdo = 0 clk 14: tms = 1, tdo = 0

(5) TAP to SHIFT-DR clk 15: tms = 0, tdo = 0 clk 16: tms = 0, tdo = 0

(6) Shift out 8 bits, 0x55 to see if it comes back on device's TDO clk 17: tms = 0, tdo = 1 clk 18: tms = 0, tdo = 0 clk 19: tms = 0, tdo = 1 clk 20: tms = 0, tdo = 0 clk 21: tms = 0, tdo = 1 clk 22: tms = 0, tdo = 0 clk 23: tms = 0, tdo = 1 clk 24: tms = 1, tdo = 0

(7) Move TAP to Select-DR-Scan state ready for next operation clk 25: tms = 1, tdo = 0 clk 26: tms = 1, tdo = 0

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Paul Taylor
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I now have this working - the method in my OP was correct.

After spending time trying to find the problem, I should have known that as soon as I post a question I would fix it - must remember this next time ;-)

Regards,

Paul.

Reply to
Paul Taylor

Please: What was wrong?

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Tauno Voipio
tauno voipio (at) iki fi
Reply to
Tauno Voipio

It was a hardware problem - a simple mistake (they always are) and I would be too embarassed to go into details!

I missed the hardware problem and I thought that the problem was how I was controlling the TAP. I haven't got the JTAG standard and was relying on documents downloaded from Xilinx, Altera and TI's websites to try and work out exactly how the TAP should be controlled. Using these docs, I wasn't completely confident that I my understanding was correct, hence the post to this newsgroup.

Regards,

Paul.

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Reply to
Paul Taylor

Missing pull-up resistors and none on-chip?

(Had it myself).

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Tauno Voipio
tauno voipio (at) iki fi
Reply to
Tauno Voipio

;-)

Look for JRunner on altera.com. It's an application to download configuration data to FPGAs. It's provided as source code and works very well (I've used it)

Jeroen

Reply to
Jeroen

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