Issues with Soft-Cores

Hi

what about pacoblaze (open-source Verilog variant of PB?)

Also JOP (something different, a hardware Java interpreter:

seems to be extensively tested.

The Plasma MIPS from Opencores is also a tested design.

Kind regards Nikolaos Kavvadias

Our ERIC5

addresses all your concerns. However, it is not free (EUR 1500,- including VHDL-code and C-compiler).

Regards,

Thomas

Thank you. I will test them. :-)

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Have you looked at the "Simple MicroBlaze Microcontroller," described in XAPP1141? I think this was Xilinx's answer to a beefier PicoBlaze with similar ease of use.

Regards, Gabor

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Hi,

Regarding OpenRISC resource usage, it's very configurable, and I believe it'll fit on most FPGAs that come on those types of development boards, even with room to spare if you turn off things like FPU, MAC, and turn down the cache sizes.

I'd be willing to help you get it up and running on your board. I help maintain a project called ORPSoC - part of the OpenRISC project - you can usually find me in #opencores on irc.freenode.net

I understand it can be a bit difficult to get this stuff up and running, and I'm interested in making it easy for new comers to get going and would like to find out exactly what parts didn't work for you when you tried things out.

Of late, the OpenRISC's GNU toolchain port has been significantly upgraded, so too various libraries, debugging utilities and its Linux kernel port (so much so it'll be in mainline before long.) I think it's not a bad platform and am interested in working to make it easier to use. Your feedback would be very useful. So please drop by the mailing lists on openrisc.net or the IRC.

Cheers,

Julius

Hello,

Do you have the XC3S200 or XC3S1000 on that board? If you got it from Digilent you would have had the option to get it with the 1000, and it might make a difference.

I also have the Spartan 3 Starter Kit personally, with the 1000. I've lent it to somebody in the office, but I don't think anyone is using it now, so I might see if I can get OpenRISC to work on it. As Julius said, there is the orpsoc project on opencores which has all of the Linux makefiles you need almost ready to go. If you don't need the external memory, and can run on block RAM, then all you need to do is update the makefiles and pin assignments, make a new set of design defines for your board and oscillator frequency, probably update the clock generator to get the right frequencies out of the PLL, and include the "ram_wb" core in the defines. The external SRAM would not be too much harder to get included, but you would need a wishbone controller written for it, which doesn't seem to exist in the IP. I asked somebody about exactly this on the OpenCores forums last week, and received some code very close to what I needed for another board, I just got it updated and am getting ready to test it out. I think it may eventually get contributed back for anyone who needs it. Otherwise I'm willing to share, anyway, so just let me know.

Alternatively, Aeroflex/Gaisler has the LEON3 soft core CPU (based on SPARC), which they offer for free if you don't need the fault tolerant version. They have a board support package for the Spartan 3 Starter Board all ready to go out of the box, and they give pretty good instructions on how to get it running, and it can be debugged directly through the stock Xilinx parallel or USB cable if that's what you happen to have. Once again, if you have the 200 version of that board, you might be out of luck, as their BSP supports the 1000, and I don't know if it would fit in the 200 or not.

Am 25.07.11 13:11, schrieb GrizzlySteve:

Definitely no. With limited peripherie (e.g. w/o MMU) it is usable on Spartan3 1000.

For a really small soft-core (with gcc support) take a look at the ZPU.

regards, Bart