According to the Virtex 4 data sheet, the setup/hold window widens considerably when using non-zero IDELAY delay (either in a normal input block or as part of ISERDES)...
For example, for a -10 part, DDR mode, setup 8.84, hold -6.51 (p28 of data sheet) gives a minimum data valid window (assuming perfect clk alignment,no jitter, etc) of 2.23ns, meaning the clk frequency for DDR data must be much less than 224MHz... seemingly somewhat less than might be implied from Table 15.
These setup and hold are defined for "D pin" with respect to "CLK". Assuming that "D pin" refers to the D pin top left of Fig 8.1, p352 of Virtex 4 user guide, this seems meaningless if the IDELAY is used to delay the data (e.g to compensate for skew of the bus on the PCB). Should these values be shifted according to the delay applied by the IDELAY, or do they in fact these values apply to D and CLK of the register flip flops themselves AFTER the IDELAY - e.g as shown IFF1 etc towards the right of Fig 7.1 p309?
I would be grateful for any clarification as I can't work it out from the datasheet!
Many thanks
Tom