Hi,
I am new to FPGA design and especially to Xilinx EDK. How does the HWICAP module (on Virtex-II and Virtex-II Pro) accesses its BRAM? Do I have to assign BRAM to my design (with EDK) or is the HWICAP module connected to a dedicated BRAM-block implicitly? Thanks for your help :)
Chris
"Christoph Lauer" schrieb im Newsbeitrag news: snipped-for-privacy@news.dfncis.de...
none of the above (not directly) HWICAP provides the access to ICAP primitive that again allows full access to the configuration interface. Those you can read write the config bit (including BRAMs). There is no need (and no possible) to connect the BRAMs to HWICAP, the ICAP can access all the FPGA configuration data anyway.
Antti
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