Hi,
I designed a 7th order FIR filter using MATLAB fdatool and obtained the VHDL code using the HDL Coder. I think that in the following part of the code there is a problem (Delay pipe line is an 8 element array, whose elements are 16 bit vectors. filter_in is a 16 bit vector):
IF reset = '1' THEN delay_pipeline(0 TO 7) (OTHERS => '0')); ELSIF clk'event AND clk = '1' THEN IF clk_enable = '1' THEN delay_pipeline(0)