HardCopy cost

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Does anyone know what the basic costs are of doing an Altera HardCopy cycle?
If, say I had a Stratix EP1S40 design that I wanted to make using HardCopy,
would there be an initial set cost then a low cost per device? If so what
would the costs be?

TIA,

Roger.



Re: HardCopy cost
Hi Roger,

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Yep. There's an NRE for the conversion process and the protos, then a
greatly reduced price per production device. Note that the HC1S devices are
not all 100% equivalent to their EP1S counterparts - try to migrate your
design to a HC1S part in Quartus first.

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Contact your local Altera salesperson for this. There's no price list for
these projects.

Best regards,



Ben


Re: HardCopy cost
Thanks Ben, I'll take what you've said on board.

Rog.

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Re: HardCopy costs- the hidden ones
All:

Proceed with extreme CAUTION!

Stratix-2 Hardcopy is offered in two flavors:

1. One that is pin compatible with the FPGA but doesn’t offer
significant die-size and price reduction and
2. The other that has a larger die size reduction (i.e. cost reduction),
but does not maintain pin compatibility with the standard FPGA.

This kind of incompatibility between Altera’s FPGAs and their Hardcopy
cousins is prevalent across product families. Across many devices in the
Stratix family for instance, there exists a mismatch (between the
standard FPGA and the Hardcopy version) in memory blocks, user I/Os and
number of PLLs. These constraints can significantly hamper the
‘conversion’ process and present customers with nasty surprises at a
critical juncture. The net result is higher development costs, unit cost
and delayed time to market.

Austin

Re: HardCopy costs- the hidden ones
Austin,

I'm in a cranky mood due to dealing with a spuriously failing motherboard
and this knee-jerk post of yours doesn't help either.

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Roger is talking about a Stratix-1, which has a well established and proven
design flow. Hardcopy II is not even fully there yet, as far as I, a lowly
disti FAE from a postage-stamp-sized country, am aware of.

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I'm even polite enough to quote you...

That's exactly why the HC 'virtual' parts were introduced into Quartus about
a year and a half ago. If a customer has a hunch (s)he may want to go for
Hardcopy later on, these devices can be used to test pin compatibility,
timing and resource usage. If aforementioned customer runs into any
incompatibilities at a critical juncture they have either (1) not listened
to their Altera FAE, (2) not used the HC1Sxxx virtual device for
prototyping, (3) use asynchronous design techniques, (4) not read the
_very_ detailed design signoff checklist or (5) any of combination of the
above.

There may be more sources of problems, but all of these fall into the
category 'didn't we tell you?'. Altera is very focused on having Hardcopy
designs to run first time and provides very strict design rules to adhere
to before accepting a design for conversion.

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Fuddyfuddyfuddy....

Note that I'm not making snide remarks about Xilinx's low-cost volume
product. I could, but I won't.

Urgh... hope I'm in a better mood tomorrow...



Ben


Re: HardCopy cost
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are


Atmel has a similar program called ULC and that can be used
regardless if it is Altera/Xilinx or whatever.
You need to supply design data, test vectors and an order.
If the design does not verify, using the test vectors, the customer does not
pay anything,
The ULC  may or may not involve an NRE depending on technology and/or
business level.

--
Best Regards,
Ulf Samuelsson.
We've slightly trimmed the long signature. Click to see the full one.
Re: HardCopy cost
Thanks for everyone's contributions. I've been looking on the Altera web
site and found from putting figures into a cost calculator that the NRE is
$195,000 with a cut in the unit cost of up to 80%. That's how I read it
anyway.

Rog.


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