Hi all,
What is good practise when resetting Virtex-II ?
What I have done is to use the startup_virtex2 block. With the GSR pin connected to a nand gate (done in VHDL). The arguments for the nand gate are the locked signal from my DCM and the external reset signal (active low and supplied from a microprocessor). This reset signal is sampled with the external system clock with a DF before an IBUF. My intention is not to clock my design before the DCM has locked. The system clock is also connected via an IBUFG to the CLKIN of the DCM. The RST pin is asserted with a delayed signal (four FD clocked with the external system clock).
Things I have lately noticed is that my running average filter which consists of SRLs does not seem to be initializing to the INIT values and thus an bias is added to the predicted level of the average.
Errorus behaviour is noticed sometimes after power on. Therefore I suspect there is something wrong with my approach.
Any feedback is appreciated. /Rick