Hi FPGA people,
I am trying to map my VHDL design on a Lattice-EC FPGA. (LFEC20E-5F672CES)
The following error warning occurs:
********************************* Map checkpoint failed. Design's logic delay (97 percent of total delay) exceeds the 60 percent limit set in the map checkpoint options ********************************* Process Stopped.Done: failed with exit code: 0001.
Unfortunately there is no direct "double click" HELP for this error message and I could not find any hint in the HELP menu.
Has someone of you any idea what this message could mean ?
Thank you in advance.
Rgds Andrés