Hi Guys,
I have written program in a way that I have logic which is being already download in to FPGA( PCI ). In my C code I am using API function to write to FPGA and then on the same bus but using different Address I am reading the values out of FPGA. What I have in my C code that I have used Sleep()command make pause then to execite the next statement which is read fucntion. But If I change time in sleep command than I am getting different values. It means that inside the FPGA in evertying clock cycle the value the signal which I am reading is changing all the time. Also in my VHDL code I haven't got anything which makes the values to change as time passes. And also according to the simulation I have a stable output as well. Could any body tell me how to do this properly to get stable output or if some one has done this before then please give me some hint to sort out this prob.
Cheers
Isaac