When DCM gets proper input clock, LOCKED signal is asserted and it works fine. It behaves correctly when the input clock changes are too wide to maintain the lock: in this situation LOCKED signal gets de-asserted. BUT in the situation when the input clock stops LOCKED signal is not de-asserted and stay asserted. My question is: does LOCKED signal in Spartan3 DCM require any clock at the input to be de-asserted?
All comments are welcome, Regards Wojtek
Hi Wojtek, If you read the user guide, you'll find that the LOCKED signal does need a clock. Maybe signal STATUS(1) is what you need, 'CLKIN stopped'. Again, you'll need to read the user guide to find this out! Cheers, Syms. p.s. Have you read the user guide? ;-)
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Hi,
Assuming that the DCM is basically the same as the one in a Virtex-2, it does need a clock signal. It's logic if you think about it: the DCM is clocked by it's input clock to make it work, so to change an output flipflop, you will need clock transitions.
If you have another clock in your design, you can easily build a small circuit that will monitor the presence of your input clock to reset the DCM when it stops. If you don't have another clock, you might build a self oscilating circuit in your fpga (see other threads in this group). Of course, you may have other options, depending on your environment (software, cable inserted signal, an external clock monitoring device, ...).
Regards, Alvin Andries.
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