what to do with the DCM locked signal?

Hi, I have a design (basically a FIR filter) that is clocked by the output of a DCM. I understand that I should not do anything before the locked signal goes high. However, what is the right way to do this?

I also have a small state machine that resets the FIR filter, sets some stuff, and then enable everything. The state machine is also clocked by the output of the DCM (it is the only clock of the design). Should I use the locked signal as an asynchronous reset of the state machine so that nothing happens before locked goes high? I wonder if this is what people do, or if there is an easier way. Thanks, David

Reply to
Dave
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Yes - use the locked signal as an asynchronous reset. That will keep your logic in a known state until the frequency is stable.

Another thought is to latch the falling edge transitions in an error flag so that if your DCM goes unlocked when you don't expect it to, you can correct / cleanup with software.

Chris

Reply to
Chris Alexander

Thanks for the answer. However, if I use the locked signal as asynchronous reset, any glitch will reset the whole state machine. Since there are no other clock in the design, I won't be able to reset the DCM and start everything again...I'm not sure I understand your second statement about latching the falling edge. Even if I generate a flag, I don't see how I would reset the DCM. Thanks, David

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Reply to
Dave

U¿ytkownik "Dave" napisa³ w wiadomo¶ci news: snipped-for-privacy@comcast.com...

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Hi!

  1. Delay the lock in the shift register
  2. Latch a lock transition to get a clock enable
  3. and use clock enable to your master state machine
  4. repeat for any clock coming from DCM

Rafal J.

Reply to
Rafal Jastrzebski

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