Connecting two buses in Xilinx ISE

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I am new to FPGA's and am designing my first circuit in Xilinx ISE.

I have two 'building block' symbols on my schematic. The first has a 16-bit wide
output, the second has a 16-bit wide input.

Is there an easy way to connect the two buses in one fell swoop, or do I have to
add 16 wires to my schematic?

Re: Connecting two buses in Xilinx ISE
Hi Nevo,
just add a wire between the bus output and input. It automaticly becomes
a bus of the correct width.

When you check the properties the net neme shuld be something like
XLNI_1(15:0)
which is a default name. You can change the name as you like, but should
  keep the bus delimiter unchanged.

have a nice synthesis
   Eilert


Nevo schrieb:
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wide output, the second has a 16-bit wide input.
Quoted text here. Click to load it
to add 16 wires to my schematic?

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