Beginner help with VHDL, Xilinx 9536XL, and ISE7.1

Bingo. That fixed everything. After downloading the 7.1.04 update, which was something like 325 megabytes, nearly as big as the full download, everything is working fine. My counter counts right, the outputs aren't inverted, and I can even directly assign pins to a value and have it work.

I spent a long time a couple nights ago searching their whole knowledge base section and reading everything I could find on the 9500 family CPLDs and never found this information. I only found it after I went to the download page for the service pack, and found the link that said something like "read this before installing" and somewhere in there was a list of what the update fixed, and in there was a short sentence or two saying that it fixed an issue with CPLD outputs being inverted. It never did mention fixing the problem where I couldn't directly assign a pin to 1 or 0 and have it work. Either way it came out as a high.

Right now, there isn't much I can say in polite company about how this makes me feel. This bug has cost me several days time. If I had been working on a real project at work, instead of hobby tinkering at home, it would have cost the company a lot of money in engineering time.

I think it is rather irresponsible of them to not at least have a notice on the download page for 7.1 saying you NEED the update to

7.1.04 if you are using CPLDs. And what they really should have done is taken down the 7.1 update and replaced it with a 7.1.04 full download, and also have the 7.1.04 update available for those who already have 7.1 installed.

Many thanks to you and to everyone else who posted their ideas.

Bingo. That fixed everything. After downloading the 7.1.04 update, which was something like 325 megabytes, nearly as big as the full download, everything is working fine. My counter counts right, the outputs aren't inverted, and I can even directly assign pins to a value and have it work.

I spent a long time a couple nights ago searching their whole knowledge base section and reading everything I could find on the 9500 family CPLDs and never found this information. I only found it after I went to the download page for the service pack, and found the link that said something like "read this before installing" and somewhere in there was a list of what the update fixed, and in there was a short sentence or two saying that it fixed an issue with CPLD outputs being inverted. It never did mention fixing the problem where I couldn't directly assign a pin to 1 or 0 and have it work. Either way it came out as a high.

Right now, there isn't much I can say in polite company about how this makes me feel. This bug has cost me several days time. If I had been working on a real project at work, instead of hobby tinkering at home, it would have cost the company a lot of money in engineering time.

I think it is rather irresponsible of them to not at least have a notice on the download page for 7.1 saying you NEED the update to

7.1.04 if you are using CPLDs. And what they really should have done is taken down the 7.1 update and replaced it with a 7.1.04 full download, and also have the 7.1.04 update available for those who already have 7.1 installed.

Many thanks to you and to everyone else who posted their ideas.

I almost did that, but not quite. :-)

The first time I got a project to go through the synthesize and fit I generated a programming file, and I was about to double click on Configure Device (iMPACT) and I suddenly thought "How does it know what pins I want my signals on?" :-) So I looked at the ISE quick start tutoral I had gone through a few weeks back when I first downloaded and installed ISE and figured out how to create UCF.

I almost did that, but not quite. :-)

The first time I got a project to go through the synthesize and fit I generated a programming file, and I was about to double click on Configure Device (iMPACT) and I suddenly thought "How does it know what pins I want my signals on?" :-) So I looked at the ISE quick start tutoral I had gone through a few weeks back when I first downloaded and installed ISE and figured out how to create UCF.

Bingo. That fixed everything. After downloading the 7.1.04 update, which was something like 325 megabytes, nearly as big as the full download, everything is working fine. My counter counts right, the outputs aren't inverted, and I can even directly assign pins to a value and have it work.

I spent a long time a couple nights ago searching their whole knowledge base section and reading everything I could find on the 9500 family CPLDs and never found this information. I only found it after I went to the download page for the service pack, and found the link that said something like "read this before installing" and somewhere in there was a list of what the update fixed, and in there was a short sentence or two saying that it fixed an issue with CPLD outputs being inverted. It never did mention fixing the problem where I couldn't directly assign a pin to 1 or 0 and have it work. Either way it came out as a high.

Right now, there isn't much I can say in polite company about how this makes me feel. This bug has cost me several days time. If I had been working on a real project at work, instead of hobby tinkering at home, it would have cost the company a lot of money in engineering time.

I think it is rather irresponsible of them to not at least have a notice on the download page for 7.1 saying you NEED the update to

7.1.04 if you are using CPLDs. And what they really should have done is taken down the 7.1 update and replaced it with a 7.1.04 full download, and also have the 7.1.04 update available for those who already have 7.1 installed.

Many thanks to you and to everyone else who posted their ideas.

...the same thing I said several times before.

It looks like my original posting attempts through google groups finally showed up after 3 days. Sorry about the double or triple posts. It won't happen again now that I have a real newsreader setup.

You're welcome. When I read that your outputs were inverted I knew what the problem was immediately.

I lost about a week's work on this one last year and really tore into the Xilinx FAEs about not posting the patch directly on the download page. It is precisely this sort of attitude by Xilinx that has me using Altera for all new designs (start the Xilinx vs. Altera debate!).

Marc

snipped-for-privacy@gmail.com wrote:

Yes, they do seem to have lowered emphasis on CPLD - Xilinx's are now the oldest families on the market, with both Altera & Lattice having newer CPLD families. The OP should stick with the SW that works, but I'd also suggest future download of the V8.1 into a parallel install, just to see what they have added - and it is quick to go back... Good SW version control, archives the tools with the designs, and this is another example of why this matters... Since the OP knows ABEL, but is new to both Xilinx tools, and their CPLDs, I'd also suggest some parallel ABEL code, just to check 'what's possible', if a similar issue occurs again...

-jg

Something like 6 months ago, the first time I tried to start up this home project (other events conspired against me and I only recently got back to it) I was going to go with Altera. I downloaded and installed their design software and started working with it a little bit.

I switched to Xilinx when I found that the Altera software locked onto your MAC address and wouldn't run if it couldn't find the matching MAC. At the time the system I was using had two ethernet adapters and I was enabling one or the other depending on which of two different networks I wanted to connect to. But when I had the "wrong" adapter enabled the software wouldn't run.

I can see the purpose in things like this to protect from piracy of expensive design software, but this was the FREE version. It doesn't need protecting...