Can anyone translate following for me. I found this as a default value into one of the slice blocks in system generator for xilinx FPGA. This block actually decode the address from the bus
32-ceil(log2(C_HIGH-C_BASE))
I am not sure but it seems:
a) C_HIGH-C_BASE seems to be the length of the adress range
b) applying log2 gives us the floating point value representing the "number of bits" needed to decode the addresses within the block.
c) the number calculated might have decimals, so we apply 32-ceil, giving as (I suppose!) an integer of 32 bits that is equal to the value above, or the lesser one greater than the number above.
Finally, we get the number of bits needed to decode the addresses with the address range.
For instance:
C_BASE= 0x0010000 C_HIGH= 0x00101C0
C_HIGH-C_BASE= 0x1C0
log2(...)=8.807355
32-ceil(...)=9Lower 9 bits of the address bus are needed to decode internal address range, higher 23 bits must be identified for equality to select the block:
address is in block: (address&0xFFFFFE00)==0x0010000 address within block: address&0x1FF
Best regards,
Zara
Note: Too sleepy this morning. Take a look at Tauno Voipio answer instead of mine So sorry.
zara
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