Hi, all,
I'm building a lock-in that needs to run for exactly 15 cycles and then stop, and have nonoverlapping switch waveforms with enough dead time to allow the input signal to settle.
It's an easy job in MSI, but since I have the opportunity I'd like to do it a bit less old-school, using a CPLD.
Xilinx's CPLD setup is _six_gigabytes_, and only lets you install it once, citing all sorts of export regs and so on. What a steaming pile.
There are a few open-source Verilog compiler/simulators, it seems.
Anybody have a favourite? Windows preferred, because that's what I run on my usual laptop.
Thanks
Phil Hobbs