Texas Instruments TMS320F2812 datasheet: 8.12.5.4.3 STANDBY Mode Timing Requirements

8.12.5.4.3 STANDBY Mode Timing Requirements

(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.

8.12.5.4.4 STANDBY Mode Switching Characteristics

(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the wake-up) signal involves additional latency.

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A. IDLE instruction is executed to put the device into STANDBY mode. B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below before being turned off: * 16 cycles, when DIVSEL = 00 or 01 * 32 cycles, when DIVSEL = 10 * 64 cycles, when DIVSEL = 11

This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in progress and its access time is longer than this number, then it will fail. It is recommended that STANDBY mode be entered from SARAM without an XINTF access in progress. C. Clocks to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. D. The external wake-up signal is driven active. E. After a latency period, the STANDBY mode is exited. F. Normal execution resumes. The device will respond to the interrupt (if enabled).

Figure 8-20. STANDBY Entry and Exit Timing

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8.12.5.4.5 HALT Mode Timing Requirements

8.12.5.4.6 HALT Mode Switching Characteristics

A. IDLE instruction is executed to put the device into HALT mode. B. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly. C. Clocks to the peripherals are turned off and the internal oscillator and PLL are shut down. The device is now in HALT mode and consumes absolute minimum power. D. When XNMI is driven active, the oscillator is turned on; but the PLL is not activated. The pulse duration of 2tc(Cl) is applicable when an external oscillator is used. If the internal oscillator is used, the oscillator wake-up time should be added to this parameter. E. When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 X1/XCLKIN cycles. F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now exited. G. Normal operation resumes. H. XCLKOUT = SYSCLKOUT

Figure 8-21. HALT Wakeup Using XNMI

8.12.5.5 Serial Peripheral Interface (SPI) Master Mode Timing

Section 8.12.5.5.1 lists the master mode timing (clock phase = 0) and Section 8.12.5.5.2 lists the master mode timing (clock phase = 1). Figure 8-22 and Figure 8-23 show the timing waveforms.

8.12.5.5.1 SPI Master Mode External Timing (Clock Phase = 0)

(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)

(3) tc(LCO) = LSPCLK cycle time

(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.

(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).

Figure 8-22. SPI Master Mode External Timing (Clock Phase = 0)

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8.12.5.5.2 SPI Master Mode External Timing (Clock Phase = 1)

(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.

(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.

(4) tc(LCO) = LSPCLK cycle time

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

Figure 8-23. SPI Master Mode External Timing (Clock Phase = 1)

8.12.5.6 Serial Peripheral Interface (SPI) Slave Mode Timing

Section 8.12.5.6.1 lists the slave mode timing (clock phase = 0) and Section 8.12.5.6.2 lists the slave mode timing (clock phase = 1). Figure 8-24 and Figure 8-25 show the timing waveforms.

8.12.5.6.1 SPI Slave Mode External Timing (Clock Phase = 0)

(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

(3) tc(LCO) = LSPCLK cycle time

(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

Figure 8-24. SPI Slave Mode External Timing (Clock Phase = 0)

8.12.5.6.2 SPI Slave Mode External Timing (Clock Phase = 1)

(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX

Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

Figure 8-25. SPI Slave Mode External Timing (Clock Phase = 1)

8.12.5.7 External Interface (XINTF) Timing

Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 8-3 shows the relationship between the parameters configured in the XTIMING register and the duration of the pulse in terms of XTIMCLK cycles.

Table 8-3. Relationship Between Parameters Configured in XTIMING and Duration of Pulse

(1) tc(XTIM) – Cycle time, XTIMCLK

(2) WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY (USEREADY = 0), then WS = 0.

Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These requirements are in addition to any timing requirements as specified by that device’s data sheet. No internal device hardware is included to detect illegal settings.

8.12.5.7.1 USEREADY = 0

If the XREADY signal is ignored (USEREADY = 0), then:

1. Lead: LR ≥ tc(XTIM) LW ≥ tc(XTIM)

These requirements result in the following XTIMING register configuration restrictions (no hardware to detect illegal XTIMING configurations):

Examples of valid and invalid timing when not sampling XREADY (no hardware to detect illegal XTIMING configurations):

TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1 TMS320F2812, TMS320F2812-Q1

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8.12.5.7.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)

If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then:

1. Lead: LR ≥ t${c(XTIM)}$ LW ≥ t${c(XTIM)}$
2. Active: AR ≥ 2 × t${c(XTIM)}$ AW ≥ 2 × t${c(XTIM)}$

NOTE: Restriction does not include external hardware wait states.

These requirements result in the following XTIMING register configuration restrictions (no hardware to detect illegal XTIMING configurations):

Examples of valid and invalid timing when using synchronous XREADY (no hardware to detect illegal XTIMING configurations):

8.12.5.7.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)

If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1, READYMODE = 1), then:

1. Lead:

   • LR ≥ tc(XTIM)
   • LW ≥ tc(XTIM)

2. Active:

   • AR ≥ 2 × tc(XTIM)
   • AW ≥ 2 × tc(XTIM)

   NOTE: Restriction does not include external hardware wait states

3. Lead + Active:

   • LR + AR ≥ 4 × tc(XTIM)
   • LW + AW ≥ 4 × tc(XTIM)

   NOTE: Restriction does not include external hardware wait states

These requirements result in the following XTIMING register configuration restrictions (no hardware to detect illegal XTIMING configurations):

or (no hardware to detect illegal XTIMING configurations):

Examples of valid and invalid timing when using asynchronous XREADY (no hardware to detect illegal XTIMING configurations):

TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1

TMS320F2812, TMS320F2812-Q1

Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 8-4.

Table 8-4. XINTF Clock Configurations

The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 8-26.

(A) Default value after reset

Figure 8-26. Relationship Between XTIMCLK and SYSCLKOUT

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8.12.5.8 XINTF Signal Alignment to XCLKOUT

For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock XTIMCLK. Strobes such as \overlineXRD, \overlineXWE, and zone chip-select ( \overlineXZCS ) change state in relationship to the rising edge of XTIMCLK. The external clock, XCLKOUT, can be configured to be either equal to or one-half the frequency of XTIMCLK.

For the case where XCLKOUT = XTIMCLK, all of the XINTF strobes will change state with respect to the rising edge of XCLKOUT. For the case where XCLKOUT = one-half XTIMCLK, some strobes will change state either on the rising edge of XCLKOUT or the falling edge of XCLKOUT. In the XINTF timing tables, the notation XCOHL is used to indicate that the parameter is with respect to either case; XCLKOUT rising edge (high) or XCLKOUT falling edge (low). If the parameter is always with respect to the rising edge of XCLKOUT, the notation XCOH is used.

For the case where XCLKOUT = one-half XTIMCLK, the XCLKOUT edge with which the change will be aligned can be determined based on the number of XTIMCLK cycles from the start of the access to the point at which the signal changes. If this number of XTIMCLK cycles is even, the alignment will be with respect to the rising edge of XCLKOUT. If this number is odd, then the signal will change with respect to the falling edge of XCLKOUT. Examples include the following:

• Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT. This is because all XINTF accesses begin with respect to the rising edge of XCLKOUT. Examples:

  • XZCSL Zone chip-select active-low
  • XRNWL XR/ \overlineW active-low

• Strobes that change at the beginning of the active period will align to the rising edge of XCLKOUT if the total number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK cycles is odd, then the alignment will be with respect to the falling edge of XCLKOUT. Examples:

  • XRDL \overlineXRD active-low
  • XWEL \overlineXWE active-low

• Strobes that change at the beginning of the trail period will align to the rising edge of XCLKOUT if the total number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If the number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will be with respect to the falling edge of XCLKOUT. Examples:

  • XRDH \overlineXRD inactive-high
  • XWEH \overlineXWE inactive-high

• Strobes that change at the end of the access will align to the rising edge of XCLKOUT if the total number of lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number of lead + active + trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will be with respect to the falling edge of XCLKOUT. Examples:

  • XZCSH Zone chip-select inactive-high
  • XRNWH XR/ \overlineW inactive-high

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8.12.5.9 External Interface Read Timing

8.12.5.9.1 External Memory Interface Read Switching Characteristics

(1) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.

8.12.5.9.2 External Memory Interface Read Timing Requirements

(1) LR = Lead period, read access. AR = Active period, read access. See Table 8-3.

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A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle before an access to meet this requirement.

B. During alignment cycles, all signals will transition to their inactive state.

C. For USEREADY = 0, the external XREADY input signal is ignored.

D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.

Figure 8-27. Example Read Access

XTIMING register parameters used for this example:

(1) N/A = “Don’t care” for this example

8.12.5.10 External Interface Write Timing

8.12.5.10.1 External Memory Interface Write Switching Characteristics

(1) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.

(2) TW = Trail period, write access. See Table 8-3.

A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle before an access to meet this requirement.

B. During alignment cycles, all signals will transition to their inactive state.

C. For USEREADY = 0, the external XREADY input signal is ignored.

D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.

Figure 8-28. Example Write Access

XTIMING register parameters used for this example:

(1) N/A = "Don't care" for this example

8.12.5.11 External Interface Ready-on-Read Timing With One External Wait State

8.12.5.11.1 External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)

(1) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.

8.12.5.11.2 External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)

(1) LR = Lead period, read access. AR = Active period, read access. See Table 8-3.

8.12.5.11.3 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)

(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 8-29: E = (XRDLEAD + XRDACTIVE) tc(XTIM) When first sampled, if XREADY (synchronous) is found to be high, then the access will complete. If XREADY (synchronous) is found to be low, it will be sampled again each tc(XTIM) until it is found to be high. For each sample (n), the setup time (D) with respect to the beginning of the access can be calculated as: D = (XRDLEAD + XRDACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL where n is the sample number (n = 1, 2, 3, and so forth).

8.12.5.11.4 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)

(1) The first XREADY (asynchronous) sample occurs with respect to E in Figure 8-30: E = (XRDLEAD + XRDACTIVE – 2) tc(XTIM) When first sampled, if XREADY (asynchronous) is found to be high, then the access will complete. If XREADY (asynchronous) is found to be low, it will be sampled again each tc(XTIM) until it is found to be high. For each sample, setup time from the beginning of the access can be calculated as: D = (XRDLEAD + XRDACTIVE – 3 + n) tc(XTIM) – tsu(XRDYAsynchL)XCOHL

where n is the sample number (n = 1, 2, 3, and so forth).

Legend:

■■■■■■■■ = Don’t care. Signal can be high or low during this time.

A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle before an access to meet this requirement.

B. During alignment cycles, all signals will transition to their inactive state.

C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.

D. For each sample, setup time from the beginning of the access (D) can be calculated as: D = (XRDLEAD + XRDACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL

E. Reference for the first sample is with respect to this point E = (XRDLEAD + XRDACTIVE) tc(XTIM) where n is the sample number (n = 1, 2, 3, and so forth).

Figure 8-29. Example Read With Synchronous XREADY Access

XTIMING register parameters used for this example:

(1) N/A = “Don’t care” for this example

Legend: □□□□□□□ = Don’t care. Signal can be high or low during this time.

A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle before an access to meet this requirement.

B. During alignment cycles, all signals will transition to their inactive state.

C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.

D. For each sample, setup time from the beginning of the access can be calculated as: D = (XRDLEAD + XRDACTIVE – 3 + n) tc(XTIM) – tsu(XRDYAsynchL)XCOHL where n is the sample number (n = 1, 2, 3, and so forth).

E. Reference for the first sample is with respect to this point: E = (XRDLEAD + XRDACTIVE – 2) tc(XTIM)

Figure 8-30. Example Read With Asynchronous XREADY Access

XTIMING register parameters used for this example:

(1) N/A = “Don’t care” for this example

8.12.5.12 External Interface Ready-on-Write Timing With One External Wait State

8.12.5.12.1 External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)

(1) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.

(2) TW = trail period, write access. See Table 8-3.

8.12.5.12.2 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)

(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 8-31:

E = (XWRLEAD + XWRACTIVE) tc(XTIM)

When first sampled, if XREADY (synchronous) is found to be high, then the access will complete. If XREADY (synchronous) is found to be low, it will be sampled again each tc(XTIM) until it is found to be high.

For each sample, setup time from the beginning of the access can be calculated as:

D = (XWRLEAD + XWRACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL

where n is the sample number (n = 1, 2, 3, and so forth).

8.12.5.12.3 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)

(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 8-32:

E = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)

When first sampled, if XREADY (asynchronous) is found to be high, then the access will complete. If XREADY (asynchronous) is found to be low, it will be sampled again each tc(XTIM) until it is found to be high.

For each sample, setup time from the beginning of the access can be calculated as:

D = (XWRLEAD + XWRACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL

where n is the sample number (n = 1, 2, 3, and so forth).

Legend: □□□□□□□□ = Don’t care. Signal can be high or low during this time.

A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle before an access to meet this requirement.

B. During alignment cycles, all signals will transition to their inactive state.

C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.

D. For each sample, setup time from the beginning of the access can be calculated as: D = (XWRLEAD + XWRACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL where n is the sample number (n = 1, 2, 3 and so forth).

E. Reference for the first sample is with respect to this point E = (XWRLEAD + XWRACTIVE) tc(XTIM)

Figure 8-31. Write With Synchronous XREADY Access

XTIMING register parameters used for this example:

(1) N/A = “Don’t care” for this example

TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1

TMS320F2812, TMS320F2812-Q1

Legend: □□□□□□□ = Don’t care. Signal can be high or low during this time.

A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle before an access to meet this requirement. B. During alignment cycles, all signals will transition to their inactive state. C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles. D. For each sample, setup time from the beginning of the access can be calculated as: D = (XWRLEAD + XWRACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL where n is the sample number (n = 1, 2, 3 and so forth). E. Reference for the first sample is with respect to this point E = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)

Figure 8-32. Write With Asynchronous XREADY Access

XTIMING register parameters used for this example:

(1) N/A = “Don’t care” for this example

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8.12.5.13 XHOLD and XHOLDA

If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of high-impedance mode.

On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the bus and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active low.

When HOLD mode is enabled and XHOLDA is active-low (external bus grant active), the CPU can still execute code from internal memory. If an access is made to the external interface, the CPU is stalled until the XHOLD signal is removed.

An external DMA request, when granted, places the following signals in a high-impedance mode:

All other signals not listed in this group remain in their default or functional operational modes during these signal events.

TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1

8.12.5.14 XHOLD/ XHOLDA Timing

8.12.5.14.1 XHOLD/ XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)

(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance state. (2) The state of XHOLD is latched on the rising edge of XTIMCLK.

A. All pending XINTF accesses are completed. B. Normal XINTF operation resumes.

Figure 8-33. External Interface Hold Waveform

8.12.5.14.2 XHOLD/ XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)

(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance state.

(2) The state of XHOLD is latched on the rising edge of XTIMCLK.

(3) After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions will occur with respect to the rising edge of XCLKOUT. Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value specified.

A. All pending XINTF accesses are completed. B. Normal XINTF operation resumes.

Figure 8-34. XHOLD/ XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)