TMS320F281x Digital Signal Processors
1 Features
- High-performance static CMOS technology
- 150 MHz (6.67-ns cycle time)
- Low-power (1.8-V core at 135 MHz, 1.9-V core at 150 MHz, 3.3-V I/O) design
- JTAG boundary scan support
- IEEE Standard 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture
- High-performance 32-bit CPU (TMS320C28x)
- 16 × 16 and 32 × 32 MAC operations
- 16 × 16 dual MAC
- Harvard bus architecture
- Atomic operations
- Fast interrupt response and processing
- Unified memory programming model
- 4M linear program/data address reach
- Code-efficient (in C/C++ and Assembly)
- TMS320F24x/LF240x processor source code compatible
- On-chip memory
- Up to 128K × 16 flash (Four 8K × 16 and six 16K × 16 sectors)
- 1K × 16 OTP ROM
- L0 and L1: 2 blocks of 4K × 16 each Single-Access RAM (SRAM)
- H0: 1 block of 8K × 16 SRAM
- M0 and M1: 2 blocks of 1K × 16 each SRAM
- Boot ROM (4K × 16)
- With software boot modes
- Standard math tables
- External interface (F2812)
- Over 1M × 16 total memory
- Programmable wait states
- Programmable read/write strobe timing
- Three individual chip selects
- Endianness: Little endian
- Clock and system control
- On-chip oscillator
- Watchdog timer module
- Three external interrupts
- Peripheral Interrupt Expansion (PIE) block that supports 45 peripheral interrupts
- Three 32-bit CPU timers
- 128-bit security key/lock
- Protects flash/OTP and L0/L1 SRAM
- Prevents firmware reverse-engineering
- Motor control peripherals
- Two Event Managers (EVA, EVB)
- Compatible to 240xA devices
- Serial port peripherals
- Serial Peripheral Interface (SPI)
- Two Serial Communications Interfaces (SCIs), standard UART
- Enhanced Controller Area Network (eCAN)
- Multichannel Buffered Serial Port (McBSP)
- 12-bit ADC, 16 channels
- 2 × 8 channel input multiplexer
- Two Sample-and-Hold
- Single/simultaneous conversions
- Fast conversion rate: 80 ns/12.5 MSPS
- Up to 56 General-Purpose I/O (GPIO) pins
- Advanced emulation features
- Analysis and breakpoint functions
- Real-time debug via hardware
- Development tools include
- ANSI C/C++ compiler/assembler/linker
- Code Composer Studio™ IDE
- DSP/BIOS™
- JTAG scan controllers
- IEEE Standard 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture
- Low-power modes and power savings
- IDLE, STANDBY, HALT modes supported
- Disable individual peripheral clocks
- Package options
- 179-ball MicroStar BGA™ with external memory interface (GHH, ZHH) (F2812)
- 176-pin Low-Profile Quad Flatpack (LQFP) with external memory interface (PGF) (F2812)
- 128-pin LQFP without external memory interface (PBK) (F2810, F2811)
- Temperature options
- A: –40°C to 85°C (GHH, ZHH, PGF, PBK)
- S: –40°C to 125°C (GHH, ZHH, PGF, PBK)
- Q: –40°C to 125°C (PGF, PBK) (AEC-Q100 qualification for automotive applications)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
2 Applications
- Advanced Driver Assistance Systems (ADAS)
- Building automation
- Electronic point of sale
- Electric Vehicle/Hybrid Electric Vehicle (EV/HEV) powertrain
- Factory automation
- Grid infrastructure
- Industrial transport
- Medical, healthcare, and fitness
- Motor drives
- Power delivery
- Telecom infrastructure
- Test and measurement
3 Description
The TMS320F2810, TMS320F2811, and TMS320F2812-Q1 devices, members of the TMS320C28x DSP generation, are highly integrated, high-performance solutions for demanding control applications.
Throughout this document, TMS320F2810, TMS320F2811, and TMS320F2812-Q1 are abbreviated as F2810, F2811, and F2812-Q1, respectively. F281x denotes all three devices.
Device Information
| PART NUMBER(1) | PACKAGE | BODY SIZE |
|---|---|---|
| TMS320F2812ZHH | MicroStar BGA (179) | 12.0 mm × 12.0 mm |
| TMS320F2812GHH | MicroStar BGA (179) | 12.0 mm × 12.0 mm |
| TMS320F2812PGF | LQFP (176) | 24.0 mm × 24.0 mm |
| TMS320F2811PBK | LQFP (128) | 14.0 mm × 14.0 mm |
| TMS320F2810PBK | LQFP (128) | 14.0 mm × 14.0 mm |
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
Product Folder Links: TMS320F2810 TMS320F2810-Q1 TMS320F2811 TMS320F2811-Q1 TMS320F2812 TMS320F2812-Q1
4 Functional Block Diagram
Protected by the code-security module.
A. 45 of the possible 96 interrupts are used on the devices. B. XINTF is available on the F2812 device only.
Figure 4-1. Functional Block Diagram
Table of Contents
- 1 Features ........ 1
- 2 Applications ........ 2
- 3 Description ........ 2
- 4 Functional Block Diagram ........ 3
- 5 Revision History ........ 4
- 6 Device Comparison ........ 5
- 6.1 Related Products ........ 6
- 7 Terminal Configuration and Functions ........ 7
- 7.1 Pin Diagrams ........ 7
- 7.2 Signal Descriptions ........ 10
- 8 Specifications ........ 19
- 8.1 Absolute Maximum Ratings ........ 19
- 8.2 ESD Ratings – Commercial ........ 20
- 8.3 ESD Ratings – Automotive ........ 20
- 8.4 Recommended Operating Conditions ........ 21
- 8.5 Power Consumption Summary ........ 22
- 8.6 Electrical Characteristics ........ 25 8.7 Thermal Resistance Characteristics for 179-Ball
- GHH Package ........ 25 8.8 Thermal Resistance Characteristics for 179-Ball
- ZHH Package ........ 25 8.9 Thermal Resistance Characteristics for 176-Pin
- PGF Package ........ 26 8.10 Thermal Resistance Characteristics for 128-Pin
- PBK Package ........ 26
- 8.11 Thermal Design Considerations ........ 26
- 8.12 Timing and Switching Characteristics ........ 27
- 9 Detailed Description ........ 87
- 9.1 Brief Descriptions ........ 87
- 9.2 Peripherals ........ 94
- 9.3 Memory Maps ........ 126
- 9.4 Register Map ........ 131
- 9.5 Device Emulation Registers ........ 133
- 9.6 External Interface, XINTF (F2812 Only) ........ 134
- 9.7 Interrupts ........ 136
- 9.8 System Control ........ 140
- 9.9 OSC and PLL Block ........ 142
- 9.10 PLL-Based Clock Module ........ 144
- 9.11 External Reference Oscillator Clock Option ........ 144
- 9.12 Watchdog Block ........ 145
- 9.13 Low-Power Modes Block ........ 146
- 10 Applications, Implementation, and Layout ........ 147
- 10.1 TI Reference Design ........ 147
- 11 Device and Documentation Support ........ 148
- 11.1 Getting Started ........ 148 11.2 Device and Development Support Tool
- Nomenclature ........ 148
- 11.3 Tools and Software ........ 149
- 11.4 Documentation Support ........ 150
- 11.5 Support Resources ........ 151
- 11.6 Trademarks ........ 152
- 11.7 Electrostatic Discharge Caution ........ 152
- 11.8 Glossary ........ 152 12 Mechanical, Packaging, and Orderable
- Information ........ 153
- 12.1 Packaging Information ........ 153
5 Revision History
Changes from July 12, 2019 to January 14, 2021 (from Revision U (July 2019) to Revision V (January 2021))
| Page |
|---|
| • Global: Updated the numbering format for tables, figures and cross-references throughout the document..... 1 |
| • Device Comparison: Updated part numbers...................................................................................5 |
6 Device Comparison
Table 6-1 provides a summary of each device’s features.
Table 6-1. Device Comparison
| FEATURE(1) | TYPE(2) | F2810 F2810-Q1 | F2811 F2811-Q1 | F2812 F2812-Q1 |
|---|---|---|---|---|
| Instruction Cycle (at 150 MHz) | – | 6.67 ns | 6.67 ns | 6.67 ns |
| Single-Access RAM (SARAM) (16-bit word) | – | 18K | 18K | 18K |
| 3.3-V On-Chip Flash (16-bit word) | – | 64K | 128K | 128K |
| Code Security for On-Chip Flash/SARAM/OTP | – | Yes | Yes | Yes |
| Boot ROM | – | Yes | Yes | Yes |
| OTP ROM (1K x 16) | – | Yes | Yes | Yes |
| External Memory Interface | 0 | – | – | Yes |
| Event Managers A and B (EVA and EVB) | – | EVA, EVB | EVA, EVB | EVA, EVB |
| ● General-Purpose (GP) Timers | – | 4 | 4 | 4 |
| ● Compare (CMP)/PWM | 0 | 16 | 16 | 16 |
| ● Capture (CAP)/QEP Channels | 0 | 6/2 | 6/2 | 6/2 |
| Watchdog Timer | – | Yes | Yes | Yes |
| 12-Bit ADC | 0 | Yes | Yes | Yes |
| ● Channels | 16 | 16 | 16 | |
| 32-Bit CPU Timers | – | 3 | 3 | 3 |
| Serial Peripheral Interface (SPI) | 0 | Yes | Yes | Yes |
| Serial Communications Interfaces A and B (SCIA and SCIB) | 0 | SCIA, SCIB | SCIA, SCIB | SCIA, SCIB |
| Controller Area Network (CAN) | 0 | Yes | Yes | Yes |
| Multichannel Buffered Serial Port (McBSP) | 0 | Yes | Yes | Yes |
| Digital I/O Pins (Shared) | – | 56 | 56 | 56 |
| External Interrupts | – | 3 | 3 | 3 |
| Supply Voltage | – | 1.8-V Core (135 MHz), 1.9-V Core (150 MHz), 3.3-V I/O | ||
| Packaging | 128-pin PBK | Yes | Yes | – |
| 176-pin PGF | – | – | Yes | |
| 179-ball GHH | – | – | Yes | |
| 179-ball ZHH | – | – | Yes | |
| Temperature Options | A: –40°C to 85°C | – | Yes | Yes |
| S: –40°C to 125°C | – | Yes | Yes | |
| Q: –40°C to 125°C (AEC-Q100 Qualification) | – | Yes | PGF only |
(1) The TMS320F281x DSPs Silicon Errata has been posted on the Texas Instruments (TI) website. It will be updated as needed.
(2) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the C2000 Real-Time Control Peripherals Reference Guide and in the peripheral reference guides.
6.1 Related Products
For information about other devices in this family of products, see the following links:
Original Delfino™ series:
TMS320F2833x Delfino™ Microcontrollers
The F2833x series is the original Delfino MCU. It is the first C2000™ MCU that is offered with a floating-point unit (FPU). It has the first-generation ePWM timers that are used throughout the rest of the Delfino and Piccolo™ families. The 12.5-MSPS, 12-bit ADC is still class-leading for an integrated analog-to-digital converter. The F2833x has a 150-MHz CPU and up to 512KB of on-chip Flash. It is available in a 176-pin QFP or 179-ball BGA package.
Newest Delfino™ series:
TMS320F2837xD Delfino™ Microcontrollers
The F2837xD series sets a new standard for performance with dual subsystems. Each subsystem consists of a C28x CPU and a parallel control law accelerator (CLA), each running at 200 MHz. Enhancing performance are TMU and VCU accelerators. New capabilities include multiple 16-bit/12-bit mode ADCs, DAC, Sigma-Delta filters, USB, configurable logic block (CLB), on-chip oscillators, and enhanced versions of all peripherals. The F2837xD is available with up to 1MB of Flash. It is available in a 176-pin QFP or 337-pin BGA package.
TMS320F2837xS Delfino™ Microcontrollers
The F2837xS series is a pin-to-pin compatible version of F2837xD but with only one C28x-CPU-and-CLA subsystem enabled. It is also available in a 100-pin QFP to enable compatibility with the Piccolo™ TMS320F2807x series.
7 Terminal Configuration and Functions
7.1 Pin Diagrams
Figure 7-1 shows the ball locations for the 179-ball GHH and ZHH ball grid array (BGA) packages. Figure 7-2 shows the pin assignments for the 176-pin PGF low-profile quad flatpack (LQFP) and Figure 7-3 shows the pin assignments for the 128-pin PBK LQFP. Table 7-1 describes the function(s) of each pin.
Figure 7-1. TMS320F2812 179-Ball GHH/ZHH MicroStar BGA™ (Bottom View)
Figure 7-2. TMS320F2812 176-Pin PGF LQFP (Top View)
8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMS320F2810 TMS320F2810-Q1 TMS320F2811 TMS320F2811-Q1 TMS320F2812 TMS320F2812-Q1
TEXAS INSTRUMENTS www.ti.com
TMS320F2812, TMS320F2812-Q1 SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
Figure 7-3. TMS320F2810 and TMS320F2811 128-Pin PBK LQFP (Top View)
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TMS320F2810 TMS320F2810-Q1 TMS320F2811 TMS320F2811-Q1 TMS320F2812 TMS320F2812-Q1
7.2 Signal Descriptions
Table 7-1 specifies the signals on the F281x devices. All digital inputs are TTL-compatible. All outputs are 3.3 V with CMOS levels. Inputs are not 5-V tolerant. A 100-µA (or 20-µA) pullup/pulldown is used.
Table 7-1. Signal Descriptions
TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1 TMS320F2812, TMS320F2812-Q1
www.ti.com SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
Table 7-1. Signal Descriptions (continued)
| NAME | PIN NO. $^{(1)}$ 179-BALL GHH/ZHH | PIN NO. $^{(1)}$ 176-PIN PGF | PIN NO. $^{(1)}$ 128-PIN PBK | I/O/Z$^{(2)}$ | PU/PD$^{(3)}$ | DESCRIPTION |
|---|---|---|---|---|---|---|
| XMP/ MC | F1 | 17 | – | I | PD | Microprocessor/Microcomputer Mode Select. Switches between microprocessor and microcomputer mode. When high, Zone 7 is enabled on the external interface. When low, Zone 7 is disabled from the external interface, and on-chip boot ROM may be accessed instead. This signal is latched into the XINTCNF2 register on a reset and the user can modify this bit in software. The state of the XMP/ \overlineMC pin is ignored after reset. |
| \overlineXHOLD | E7 | 159 | – | I | PU | External Hold Request. \overlineXHOLD, when active (low), requests the XINTF to release the external bus and place all buses and strobes into a high-impedance state. The XINTF will release the bus when any current access is complete and there are no pending accesses on the XINTF. |
| \overlineXHOLDA | K10 | 82 | – | O/Z | – | External Hold Acknowledge. \overlineXHOLDA is driven active (low) when the XINTF has granted a \overlineXHOLD request. All XINTF buses and strobe signals will be in a high-impedance state. \overlineXHOLDA is released when the \overlineXHOLD signal is released. External devices should only drive the external bus when \overlineXHOLDA is active (low). |
| \overlineXZCS0AND1 | P1 | 44 | – | O/Z | – | XINTF Zone 0 and Zone 1 Chip Select. \overlineXZCS0AND1 is active (low) when an access to the XINTF Zone 0 or Zone 1 is performed. |
| \overlineXZCS2 | P13 | 88 | – | O/Z | – | XINTF Zone 2 Chip Select. \overlineXZCS2 is active (low) when an access to the XINTF Zone 2 is performed. |
| \overlineXZCS6AND7 | B13 | 133 | – | O/Z | – | XINTF Zone 6 and Zone 7 Chip Select. \overlineXZCS6AND7 is active (low) when an access to the XINTF Zone 6 or Zone 7 is performed. |
| \overlineXWE | N11 | 84 | – | O/Z | – | Write Enable. Active-low write strobe. The write strobe waveform is specified, per zone basis, by the Lead, Active, and Trail periods in the XTIMINGx registers. |
| XRD | M3 | 42 | – | O/Z | – | Read Enable. Active-low read strobe. The read strobe waveform is specified, per zone basis, by the Lead, Active, and Trail periods in the XTIMINGx registers. NOTE: The XRD and XWE signals are mutually exclusive. |
| XR/ \overlineW | N4 | 51 | – | O/Z | – | Read Not Write Strobe. Normally held high. When low, XR/ \overlineW indicates write cycle is active; when high, XR/ \overlineW indicates read cycle is active. |
| XREADY | B6 | 161 | – | I | PU | Ready Signal. Indicates peripheral is ready to complete the access when asserted to 1. XREADY can be configured to be a synchronous or an asynchronous input. See the timing diagrams for more details. |
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Table 7-1. Signal Descriptions (continued)
| NAME | PIN NO. (1) | I/O/Z(2) | PU/PD(3) | DESCRIPTION | ||
|---|---|---|---|---|---|---|
| 179-BALL GHH/ZHH | 176-PIN PGF | 128-PIN PBK | ||||
| JTAG AND MISCELLANEOUS SIGNALS | ||||||
| X1/XCLKIN | K9 | 77 | 58 | I | – | Oscillator Input – input to the internal oscillator. This pin is also used to feed an external clock. The 28x can be operated with an external clock source, provided that the proper voltage levels be driven on the X1/XCLKIN pin. It should be noted that the X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V) core digital power supply (VDD), rather than the 3.3-V I/O supply (VDDIO). A clamping diode may be used to clamp a buffered clock signal to ensure that the logic-high level does not exceed VDD (1.8 V or 1.9 V) or a 1.8-V oscillator may be used. |
| X2 | M9 | 76 | 57 | O | – | Oscillator Output |
| XCLKOUT | F11 | 119 | 87 | O | – | Output clock derived from SYSCLKOUT to be used for external wait-state generation and as a general-purpose clock source. XCLKOUT is either the same frequency, 1/2 the frequency, or 1/4 the frequency of SYSCLKOUT. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting bit 3 (CLKOFF) of the XINTCNF2 register to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in a high-impedance state during reset. |
| TESTSEL | A13 | 134 | 97 | I | PD | Test Pin. Reserved for TI. Must be connected to ground. |
| XRS | D6 | 160 | 113 | I/O | PU | Device Reset (in) and Watchdog Reset (out). Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs. During watchdog reset, the XRS pin will be driven low for the watchdog reset duration of 512 XCLKIN cycles. The output buffer of this pin is an open-drain with an internal pullup (100 μA, typical). If this pin is driven by an external device, it should be done using an open-drain device. |
| TEST1 | M7 | 67 | 51 | I/O | – | Test Pin. Reserved for TI. On F281x devices, TEST1 must be left unconnected. |
| TEST2 | N7 | 66 | 50 | I/O | – | Test Pin. Reserved for TI. On F281x devices, TEST2 must be left unconnected. |
Table 7-1. Signal Descriptions (continued)
| NAME | PIN NO. (1) | I/O/Z(2) | PU/PD(3) | DESCRIPTION | ||
|---|---|---|---|---|---|---|
| 179-BALL GHH/ZHH | 176-PIN PGF | 128-PIN PBK | ||||
| JTAG | ||||||
| TRST | B12 | 135 | 98 | I | PD | JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: Do not use pullup resistors on TRST; it has an internal pulldown device. TRST is an active-high test pin and must be maintained low at all times during normal device operation. In a low-noise environment, TRST may be left floating. In other instances, an external pulldown resistor is highly recommended. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. |
| TCK | A12 | 136 | 99 | I | PU | JTAG test clock with internal pullup |
| TMS | D13 | 126 | 92 | I | PU | JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. |
| TDI | C13 | 131 | 96 | I | PU | JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. |
| TDO | D12 | 127 | 93 | O/Z | – | JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) is shifted out of TDO on the falling edge of TCK. |
| EMU0 | D11 | 137 | 100 | I/O/Z | PU | Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. |
Table 7-1. Signal Descriptions (continued)
| NAME | PIN NO. (1) | I/O/Z(2) | PU/PD(3) | DESCRIPTION | ||
|---|---|---|---|---|---|---|
| 179-BALL GHH/ZHH | 176-PIN PGF | 128-PIN PBK | ||||
| EMU1 | C9 | 146 | 105 | I/O/Z | PU | Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. |
| ADC ANALOG INPUT SIGNALS | ||||||
| ADCINA7 | B5 | 167 | 119 | I | – | 8-channel analog inputs for Sample-and-Hold A. The ADC pins should not be driven before the VDDA1, VDDA2, and VDDAIO pins have been fully powered up. |
| ADCINA6 | D5 | 168 | 120 | I | – | |
| ADCINA5 | E5 | 169 | 121 | I | – | |
| ADCINA4 | A4 | 170 | 122 | I | – | |
| ADCINA3 | B4 | 171 | 123 | I | – | |
| ADCINA2 | C4 | 172 | 124 | I | – | |
| ADCINA1 | D4 | 173 | 125 | I | – | |
| ADCINA0 | A3 | 174 | 126 | I | – | |
| ADCINB7 | F5 | 9 | 9 | I | – | 8-channel analog inputs for Sample-and-Hold B. The ADC pins should not be driven before the VDDA1, VDDA2, and VDDAIO pins have been fully powered up. |
| ADCINB6 | D1 | 8 | 8 | I | – | |
| ADCINB5 | D2 | 7 | 7 | I | – | |
| ADCINB4 | D3 | 6 | 6 | I | – | |
| ADCINB3 | C1 | 5 | 5 | I | – | |
| ADCINB2 | B1 | 4 | 4 | I | – | |
| ADCINB1 | C3 | 3 | 3 | I | – | |
| ADCINB0 | C2 | 2 | 2 | I | – | |
| ADCREFP | E2 | 11 | 11 | I/O | – | ADC Voltage Reference Output (2 V). Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of 10 μF to analog ground. [Can accept external reference input (2 V) if the software bit is enabled for this mode. 1–10 μF low ESR capacitor can be used in the external reference mode.] NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is used in the system. |
| ADCREFM | E4 | 10 | 10 | I/O | – | ADC Voltage Reference Output (1 V). Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of 10 μF to analog ground. [Can accept external reference input (1 V) if the software bit is enabled for this mode. 1–10 μF low ESR capacitor can be used in the external reference mode.] NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is used in the system. |
Table 7-1. Signal Descriptions (continued)
| NAME | PIN NO. (1) | I/O/Z(2) | PU/PD(3) | DESCRIPTION | ||
|---|---|---|---|---|---|---|
| 179-BALL GHH/ZHH | 176-PIN PGF | 128-PIN PBK | ||||
| ADCRESEXT | F2 | 16 | 16 | O | – | ADC External Current Bias Resistor. Use 24.9 kΩ ± 5% for ADC clock range 1–18.75 MHz; use 20 kΩ ± 5% for ADC clock range 18.75 MHz–25 MHz. |
| ADCBGREFIN | E6 | 164 | 116 | – | – | Test Pin. Reserved for TI. Must be left unconnected. |
| AVSSREFBG | E3 | 12 | 12 | – | – | ADC Analog GND |
| AVDDREFBG | E1 | 13 | 13 | – | – | ADC Analog Power (3.3-V) |
| ADCLO | B3 | 175 | 127 | – | – | Common Low Side Analog Input. Connect to analog ground. |
| VSSA1 | F3 | 15 | 15 | – | – | ADC Analog GND |
| VSSA2 | C5 | 165 | 117 | – | – | ADC Analog GND |
| VDDA1 | F4 | 14 | 14 | – | – | ADC Analog 3.3-V Supply |
| VDDA2 | A5 | 166 | 118 | – | – | ADC Analog 3.3-V Supply |
| VSS1 | C6 | 163 | 115 | – | – | ADC Digital GND |
| VDD1 | A6 | 162 | 114 | – | – | ADC Digital 1.8-V (or 1.9-V) Supply |
| VDDAIO | B2 | 1 | 1 | – | – | 3.3-V Analog I/O Power Pin |
| VSSAIO | A2 | 176 | 128 | – | – | Analog I/O Ground Pin |
POWER SIGNALS
| VDD | H1 | 23 | 20 | – | – | 1.8-V or 1.9-V Core Digital Power Pins. See Section 8.4, Recommended Operating Conditions, for voltage requirements. | | VDD | L1 | 37 | 29 | – | – | | | VDD | P5 | 56 | 42 | – | – | | | VDD | P9 | 75 | 56 | – | – | | | VDD | P12 | – | 63 | – | – | | | VDD | K12 | 100 | 74 | – | – | | | VDD | G12 | 112 | 82 | – | – | | | VDD | C14 | 128 | 94 | – | – | | | VDD | B10 | 143 | 102 | – | – | | | VDD | C8 | 154 | 110 | – | – | | | VSS | G4 | 19 | 17 | – | – | Core and Digital I/O Ground Pins | | VSS | K1 | 32 | 26 | – | – | | | VSS | L2 | 38 | 30 | – | – | | | VSS | P4 | 52 | 39 | – | – | | | VSS | K6 | 58 | – | – | – | | | VSS | P8 | 70 | 53 | – | – | | | VSS | M10 | 78 | 59 | – | – | | | VSS | L11 | 86 | 62 | – | – | | | VSS | K13 | 99 | 73 | – | – | | | VSS | J14 | 105 | – | – | – | | | VSS | G13 | 113 | – | – | – | | | VSS | E14 | 120 | 88 | – | – | | | VSS | B14 | 129 | 95 | – | – | | | VSS | D10 | 142 | – | – | – | | | VSS | C10 | – | 103 | – | – | | | VSS | B8 | 153 | 109 | – | – | |
Table 7-1. Signal Descriptions (continued)
| NAME | PIN NO. (1) | I/O/Z(2) | PU/PD(3) | DESCRIPTION | ||
|---|---|---|---|---|---|---|
| 179-BALL GHH/ZHH | 176-PIN PGF | 128-PIN PBK | ||||
| VDDIO | J4 | 31 | 25 | – | – | 3 3-V I/O Digital Power Pins |
| VDDIO | L7 | 64 | 49 | – | – | |
| VDDIO | L10 | 81 | – | – | – | |
| VDDIO | N14 | – | – | – | – | |
| VDDIO | G11 | 114 | 83 | – | – | |
| VDDIO | E9 | 145 | 104 | – | – | |
| VDD3VFL | N8 | 69 | 52 | – | – | 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times after power-up sequence requirements have been met. |
| GPIO OR PERIPHERAL SIGNALS | ||||||
| GPIOA OR EVA SIGNALS | ||||||
| GPIOA0 - PWM1 (O) | M12 | 92 | 68 | I/O | PU | GPIO or PWM Output Pin #1 |
| GPIOA1 - PWM2 (O) | M14 | 93 | 69 | I/O | PU | GPIO or PWM Output Pin #2 |
| GPIOA2 - PWM3 (O) | L12 | 94 | 70 | I/O | PU | GPIO or PWM Output Pin #3 |
| GPIOA3 - PWM4 (O) | L13 | 95 | 71 | I/O | PU | GPIO or PWM Output Pin #4 |
| GPIOA4 - PWM5 (O) | K11 | 98 | 72 | I/O | PU | GPIO or PWM Output Pin #5 |
| GPIOA5 - PWM6 (O) | K14 | 101 | 75 | I/O | PU | GPIO or PWM Output Pin #6 |
| GPIOA6 - T1PWM_T1CMP (I) | J11 | 102 | 76 | I/O | PU | GPIO or Timer 1 Output |
| GPIOA7 - T2PWM_T2CMP (I) | J13 | 104 | 77 | I/O | PU | GPIO or Timer 2 Output |
| GPIOA8 - CAP1_QEP1 (I) | H10 | 106 | 78 | I/O | PU | GPIO or Capture Input #1 |
| GPIOA9 - CAP2_QEP2 (I) | H11 | 107 | 79 | I/O | PU | GPIO or Capture Input #2 |
| GPIOA10 - CAP3_QEP11 (I) | H12 | 109 | 80 | I/O | PU | GPIO or Capture Input #3 |
| GPIOA11 - TDIRA (I) | F14 | 116 | 85 | I/O | PU | GPIO or Timer Direction |
| GPIOA12 - TCLKINA (I) | F13 | 117 | 86 | I/O | PU | GPIO or Timer Clock Input |
| GPIOA13 - C1TRIP (I) | E13 | 122 | 89 | I/O | PU | GPIO or Compare 1 Output Trip |
| GPIOA14 - C2TRIP (I) | E11 | 123 | 90 | I/O | PU | GPIO or Compare 2 Output Trip |
| GPIOA15 - C3TRIP (I) | F10 | 124 | 91 | I/O | PU | GPIO or Compare 3 Output Trip |
| GPIOB OR EVB SIGNALS | ||||||
| GPIOB0 - PWM7 (O) | N2 | 45 | 33 | I/O | PU | GPIO or PWM Output Pin #7 |
| GPIOB1 - PWM8 (O) | P2 | 46 | 34 | I/O | PU | GPIO or PWM Output Pin #8 |
| GPIOB2 - PWM9 (O) | N3 | 47 | 35 | I/O | PU | GPIO or PWM Output Pin #9 |
| GPIOB3 - PWM10 (O) | P3 | 48 | 36 | I/O | PU | GPIO or PWM Output Pin #10 |
| GPIOB4 - PWM11 (O) | L4 | 49 | 37 | I/O | PU | GPIO or PWM Output Pin #11 |
| GPIOB5 - PWM12 (O) | M4 | 50 | 38 | I/O | PU | GPIO or PWM Output Pin #12 |
| GPIOB6 - T3PWM_T3CMP (I) | K5 | 53 | 40 | I/O | PU | GPIO or Timer 3 Output |
| GPIOB7 - T4PWM_T4CMP (I) | N5 | 55 | 41 | I/O | PU | GPIO or Timer 4 Output |
| GPIOB8 - CAP4_QEP3 (I) | M5 | 57 | 43 | I/O | PU | GPIO or Capture Input #4 |
| GPIOB9 - CAP5_QEP4 (I) | M6 | 59 | 44 | I/O | PU | GPIO or Capture Input #5 |
| GPIOB10 - CAP6_QEP12 (I) | P6 | 60 | 45 | I/O | PU | GPIO or Capture Input #6 |
| GPIOB11 - TDIRB (I) | L8 | 71 | 54 | I/O | PU | GPIO or Timer Direction |
| GPIOB12 - TCLKINB (I) | K8 | 72 | 55 | I/O | PU | GPIO or Timer Clock Input |
| GPIOB13 - C4TRIP (I) | N6 | 61 | 46 | I/O | PU | GPIO or Compare 4 Output Trip |
Table 7-1. Signal Descriptions (continued)
| NAME | PIN NO. (1) | I/O/Z(2) | PU/PD(3) | DESCRIPTION | ||
|---|---|---|---|---|---|---|
| 179-BALL GHH/ZHH | 176-PIN PGF | 128-PIN PBK | ||||
| GPIOB14 - C5TRIP (I) | L6 | 62 | 47 | I/O | PU | GPIO or Compare 5 Output Trip |
| GPIOB15 - C6TRIP (I) | K7 | 63 | 48 | I/O | PU | GPIO or Compare 6 Output Trip |
| GPIOD OR EVA SIGNALS | ||||||
| GPIOD0 - T1CTRIP_PDPINTA (I) | H14 | 110 | 81 | I/O | PU | GPIO or Timer 1 Compare Output Trip |
| GPIOD1 - T2CTRIP/ EVASOC (I) | G10 | 115 | 84 | I/O | PU | GPIO or Timer 2 Compare Output Trip or External ADC Start-of-Conversion EV-A |
| GPIOD OR EVB SIGNALS | ||||||
| GPIOD5 - T3CTRIP_PDPINTB (I) | P10 | 79 | 60 | I/O | PU | GPIO or Timer 3 Compare Output Trip |
| GPIOD6 - T4CTRIP/ EVBSOC (I) | P11 | 83 | 61 | I/O | PU | GPIO or Timer 4 Compare Output Trip or External ADC Start-of-Conversion EV-B |
| GPIOE OR INTERRUPT SIGNALS | ||||||
| GPIOE0 - XINT1_XBIO (I) | D9 | 149 | 106 | I/O/Z | – | GPIO or XINT1 or XBIO input |
| GPIOE1 - XINT2_ADCSOC (I) | D8 | 151 | 108 | I/O/Z | – | GPIO or XINT2 or ADC start-of-conversion |
| GPIOE2 - XNMI_XINT13 (I) | E8 | 150 | 107 | I/O | PU | GPIO or XNMI or XINT13 |
| GPIOF OR SPI SIGNALS | ||||||
| GPIOF0 - SPISIMOA (O) | M1 | 40 | 31 | I/O/Z | – | GPIO or SPI slave in, master out |
| GPIOF1 - SPISOMIA (I) | N1 | 41 | 32 | I/O/Z | – | GPIO or SPI slave out, master in |
| GPIOF2 - SPICLKA (I/O) | K2 | 34 | 27 | I/O/Z | – | GPIO or SPI clock |
| GPIOF3 - SPISTEA (I/O) | K4 | 35 | 28 | I/O/Z | – | GPIO or SPI slave transmit enable |
| GPIOF OR SCI-A SIGNALS | ||||||
| GPIOF4 - SCITXDA (O) | C7 | 155 | 111 | I/O | PU | GPIO or SCI asynchronous serial port TX data |
| GPIOF5 - SCIRXDA (I) | A7 | 157 | 112 | I/O | PU | GPIO or SCI asynchronous serial port RX data |
| GPIOF OR CAN SIGNALS | ||||||
| GPIOF6 - CANTXA (O) | N12 | 87 | 64 | I/O | PU | GPIO or eCAN transmit data |
| GPIOF7 - CANRXA (I) | N13 | 89 | 65 | I/O | PU | GPIO or eCAN receive data |
| GPIOF OR McBSP SIGNALS | ||||||
| GPIOF8 - MCLKXA (I/O) | J1 | 28 | 23 | I/O | PU | GPIO or McBSP transmit clock |
| GPIOF9 - MCLKRA (I/O) | H2 | 25 | 21 | I/O | PU | GPIO or McBSP receive clock |
| GPIOF10 - MFSXA (I/O) | H4 | 26 | 22 | I/O | PU | GPIO or McBSP transmit frame synch |
| GPIOF11 - MFSRA (I/O) | J2 | 29 | 24 | I/O | PU | GPIO or McBSP receive frame synch |
| GPIOF12 - MDXA (O) | G1 | 22 | 19 | I/O | – | GPIO or McBSP transmitted serial data |
| GPIOF13 - MDRA (I) | G2 | 20 | 18 | I/O | PU | GPIO or McBSP received serial data |
Table 7-1. Signal Descriptions (continued)
| NAME | PIN NO. (1) | I/O/Z(2) | PU/PD(3) | DESCRIPTION | ||
|---|---|---|---|---|---|---|
| 179-BALL GHH/ZHH | 176-PIN PGF | 128-PIN PBK | ||||
| GPIOF OR XF CPU OUTPUT SIGNAL | ||||||
| GPIOF14 - XF_XPLLDIS (O) | A11 | 140 | 101 | I/O | PU | This pin has three functions:1. XF – General-purpose output pin.2. XPLLDIS – This pin is sampled during reset to check whether the PLL must be disabled. The PLL will be disabled if this pin is sensed low. HALT and STANDBY modes cannot be used when the PLL is disabled.3. GPIO – GPIO function |
| GPIOG OR SCI-B SIGNALS | ||||||
| GPIOG4 - SCITXDB (O) | P14 | 90 | 66 | I/O/Z | – | GPIO or SCI asynchronous serial port transmit data |
| GPIOG5 - SCIRXDB (I) | M13 | 91 | 67 | I/O/Z | – | GPIO or SCI asynchronous serial port receive data |
(1) Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
(2) I = Input, O = Output, Z = High impedance
(3) PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 8.6, Electrical Characteristics Over Recommended Operating Conditions. The pullups/pulldowns are enabled in boundary scan mode.
Note
Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached recommended operating conditions. However, it is acceptable for an I/O pin to ramp along with the 3.3-V supply.