Texas Instruments TMS320F2812 datasheet: 9.2.5 Multichannel Buffered Serial Port (McBSP) Module

9.2.5 Multichannel Buffered Serial Port (McBSP) Module

The McBSP module has the following features:

• Compatible to McBSP in TMS320C54x/TMS320C55x DSP devices, except the DMA features
• Full-duplex communication
• Double-buffered data registers which allow a continuous data stream
• Independent framing and clocking for receive and transmit
• External shift clock generation or an internal programmable frequency shift clock
• A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits
• 8-bit data transfers with LSB or MSB first
• Programmable polarity for both frame synchronization and data clocks
• Highly programmable internal clock and frame generation
• Support A-bis mode
• Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected A/D and D/A devices
• Works with SPI-compatible devices
• Two 16 x 16-level FIFO for Transmit channel
• Two 16 x 16-level FIFO for Receive channel

The following application interfaces can be supported on the McBSP:

• T1/E1 framers
• MVIP switching-compatible and ST-BUS-compliant devices including:
  • MVIP framers
  • H.100 framers
  • SCSA framers
  • IOM-2 compliant devices
  • AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
  • IIS-compliant devices
• McBSP clock rate = CLKG = CLKSRG/(1 + CLKGDIV), where CLKSRG source could be LSPCLK, CLKX, or CLKR.¹

¹ Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit—20-MHz maximum.

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Figure 9-9 shows the block diagram of the McBSP module with FIFO, interfaced to the F281x version of Peripheral Frame 2.

Figure 9-9. McBSP Module With FIFO

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Table 9-9 provides a summary of the McBSP registers.

Table 9-9. McBSP Registers

TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1

TMS320F2812, TMS320F2812-Q1

Table 9-9. McBSP Registers (continued)

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Table 9-9. McBSP Registers (continued)

(1) DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.

(2) FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.

9.2.6 Serial Communications Interface (SCI) Module

The F281x devices include two serial communications interface (SCI) modules. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register.

Features of each SCI module include:

• Two external pins:
  • SCITXD: SCI transmit-output pin
  • SCIRXD: SCI receive-input pin

NOTE: Both pins can be used as GPIO if not used for SCI.

• Baud rate programmable to 64K different rates²

  $$ \text{Baud rate} = \frac{\text{LSPCLK}}{(\text{BRR} + 1) * 8} \quad \text{when BRR} \neq 0 $$

  $$ = \frac{\text{LSPCLK}}{16} \quad \text{when BRR} = 0 $$

• Data-word format

  • One start bit
  • Data-word length programmable from one to eight bits
  • Optional even/odd/no parity bit
  • One or two stop bits

• Four error-detection flags: parity, overrun, framing, and break detection

• Two wake-up multiprocessor modes: idle-line and address bit

• Half- or full-duplex operation

• Double-buffered receive and transmit functions

• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags.

  • Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty)
  • Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)

• Separate enable bits for transmitter and receiver interrupts (except BRKDT)

• Max bit rate = 75 MHz/16 = 4.688 x 10⁶ b/s

• NRZ (non-return-to-zero) format

• Ten SCI module control registers located in the control register frame beginning at address 7050h

NOTE: All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.

Enhanced features:

• Auto baud-detect hardware logic
• 16-level transmit/receive FIFO

² Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum.

The SCI port operation is configured and controlled by the registers listed in Table 9-10 and Table 9-11.

Table 9-10. SCI-A Registers

(1) These registers are new registers for the FIFO mode.

Table 9-11. SCI-B Registers

(1) Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.

(2) These registers are new registers for the FIFO mode.

Figure 9-10 shows the SCI module block diagram.

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Figure 9-10. Serial Communications Interface (SCI) Module Block Diagram

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9.2.7 Serial Peripheral Interface (SPI) Module

The F281x devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.

The SPI module features include:

• Four external pins:
  • SPISOMI: SPI slave-output/master-input pin
  • SPISIMO: SPI slave-input/master-output pin
  • SPISTE: SPI slave transmit-enable pin
  • SPICLK: SPI serial-clock pin

NOTE: All four pins can be used as GPIO, if the SPI module is not used.

• Two operational modes: master and slave

• Baud rate: 125 different programmable rates

  Baud rate = \fracLSPCLK(SPIBRR + 1) when SPIBRR ≠ 0
  = \fracLSPCLK4 when SPIBRR = 0, 1, 2, 3

Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum.

• Data word length: one to sixteen data bits
• Four clocking schemes (controlled by clock polarity and clock phase bits) include:
  • Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
  • Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
  • Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
  • Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
• Simultaneous receive and transmit operation (transmit function can be disabled in software)
• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
• Nine SPI module control registers: Located in control register frame beginning at address 7040h.

NOTE: All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.

Enhanced features:

• 16-level transmit/receive FIFO
• Delayed transmit control

The SPI port operation is configured and controlled by the registers listed in Table 9-12.

Table 9-12. SPI Registers

(1) These registers are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.

Figure 9-11 is a block diagram of the SPI in slave mode.

A. \overlineSPISTE is driven low by the master for a slave device.

Figure 9-11. Serial Peripheral Interface Module Block Diagram (Slave Mode)

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9.2.8 GPIO MUX

The GPIO Mux registers are used to select the operation of shared pins on the F281x devices. The pins can be individually selected to operate as “Digital I/O” or connected to “Peripheral I/O” signals (via the GPxMUX registers). If selected for “Digital I/O”mode, registers are provided to configure the pin direction (via the GPxDIR registers) and to qualify the input signal to remove unwanted noise (via the GPxQUAL) registers). Table 9-13 lists the GPIO Mux Registers.

Table 9-13. GPIO Mux Registers

(1) Reserved locations return undefined values and writes are ignored. (2) Not all inputs support input signal qualification. (3) These registers are EALLOW protected. This prevents spurious writes from overwriting the contents and corrupting the system.

If configured for "Digital I/O" mode, additional registers are provided for setting individual I/O signals (via the GPxSET registers), for clearing individual I/O signals (via the GPxCLEAR registers), for toggling individual I/O signals (via the GPxTOGGLE registers), or for reading/writing to the individual I/O signals (via the GPxDAT registers). Table 9-14 lists the GPIO Data Registers. For more information, see the TMS320x281x DSP System Control and Interrupts Reference Guide.

Table 9-14. GPIO Data Registers

(1) Reserved locations will return undefined values and writes will be ignored. (2) These registers are NOT EALLOW protected. The above registers will typically be accessed regularly by the user.

TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1

TMS320F2812, TMS320F2812-Q1

Figure 9-12 shows how the various register bits select the various modes of operation for GPIO function.

A. In the GPIO mode, when the GPIO pin is configured for output operation, reading the GPxDAT data register only gives the value written, not the value at the pin. In the peripheral mode, the state of the pin can be read through the GPxDAT register, provided the corresponding direction bit is zero (input mode).

B. Some selected input signals are qualified by the SYSCLKOUT. The GPxQUAL register specifies the qualification sampling period. The sampling window is 6 samples wide and the output is only changed when all samples are the same (all 0's or all 1's). This feature removes unwanted spikes from the input signal.

Figure 9-12. GPIO/Peripheral Pin Multiplexing

Note

The input function of the GPIO pin and the input path to the peripheral are always enabled. It is the output function of the GPIO pin that is multiplexed with the output path of the primary (peripheral) function. Since the output buffer of a pin connects back to the input buffer, any GPIO signal present at the pin will be propagated to the peripheral module as well. Therefore, when a pin is configured for GPIO operation, the corresponding peripheral functionality (and interrupt-generating capability) must be disabled. Otherwise, interrupts may be inadvertently triggered. This is especially critical when the PDPINTA and PDPINTB pins are used as GPIO pins, since a value of zero for GPDDAT.0 or GPDDAT.5 (PDPINTx) will put PWM pins in a high-impedance state. The CxTRIP and TxCTTRIP pins will also put the corresponding PWM pins in high impedance, if they are driven low (as GPIO pins) and bit EXTCONx.0 = 1.

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TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1

9.3 Memory Maps

LEGEND:

Only one of these vector maps - M0 vector, PIE vector, BROM vector, XINTF vector - should be enabled at a time.

A. Memory blocks are not to scale. B. Reserved locations are reserved for future expansion. Application should not access these areas. C. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both. D. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program cannot access these memory maps in program space. E. "Protected" means the order of Write followed by Read operations is preserved rather than the pipeline order. F. Certain memory ranges are EALLOW protected against spurious writes after configuration. G. Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.

Figure 9-13. F2812 Memory Map

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LEGEND: Only one of these vector maps - M0 vector, PIE vector, BROM vector - should be enabled at a time.

A. Memory blocks are not to scale. B. Reserved locations are reserved for future expansion. Application should not access these areas. C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program cannot access these memory maps in program space. D. "Protected" means the order of Write followed by Read operations is preserved rather than the pipeline order. E. Certain memory ranges are EALLOW protected against spurious writes after configuration.

Figure 9-14. F2811 Memory Map

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LEGEND:

Only one of these vector maps - M0 vector, PIE vector, BROM vector - should be enabled at a time.

A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program cannot access these memory maps in program space.
D. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.

Figure 9-15. F2810 Memory Map

Table 9-15. Addresses of Flash Sectors in F2812 and F2811

Table 9-16. Addresses of Flash Sectors in F2810

The “Low 64K” of the memory address range maps into the data space of the 240x. The “High 64K” of the memory address range maps into the program space of the 24x/240x. 24x/240x-compatible code will execute only from the “High 64K”memory area. Hence, the top 32K of Flash and H0 SRAM block can be used to run 24x/240x-compatible code (if MP/ \overlineMC mode is low) or, on the F2812, code can be executed from XINTF Zone 7 (if MP/ \overlineMC mode is high).

The XINTF consists of five independent zones. One zone has its own chip select and the remaining four zones share two chip selects. Each zone can be programmed with its own timing (wait states) and to either sample or ignore external ready signal. This makes interfacing to external peripherals easy and glueless.

Note

The chip selects of XINTF Zone 0 and Zone 1 are merged into a single chip select (XZCS0AND1); and the chip selects of XINTF Zone 6 and Zone 7 are merged into a single chip select (XZCS6AND7). See Section 9.6, External Interface, XINTF (F2812 only), for details.

Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together to enable these blocks to be “write/read peripheral block protected”. The “protected” mode ensures that all accesses to these blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports a block protection mode where a region of memory can be protected to make sure that operations occur as written (the penalty is extra cycles that are added to align the operations). This mode is programmable and, by default, it will protect the selected zones.

On the F2812, at reset, XINTF Zone 7 is accessed if the XMP/ \overlineMC pin is pulled high. This signal selects microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows the user to either boot from on-chip memory or from off-chip memory. The state of the XMP/ \overlineMC signal on reset is stored in an MP/ \overlineMC mode bit in the XINTCNF2 register. The user can change this mode in software and hence control the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are affected by XMP/ \overlineMC.

I/O space is not supported on the F2812 XINTF.

The wait states for the various spaces in the memory map area are listed in Table 9-17.

Table 9-17. Wait States

9.4 Register Map

The F281x devices contain three peripheral register spaces. The spaces are categorized as follows:

• Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 9-18.
• Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See Table 9-19.
• Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See Table 9-20.

Table 9-18. Peripheral Frame 0 Registers

(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS instruction disables writes. This prevents stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).

Table 9-19. Peripheral Frame 1 Registers

(1) The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.

Table 9-20. Peripheral Frame 2 Registers

(1) Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).

9.5 Device Emulation Registers

These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 9-21.

Table 9-21. Device Emulation Registers

9.6 External Interface, XINTF (F2812 Only)

This section gives a top-level view of the external interface (XINTF) that is implemented on the F2812 device.

The external interface is a non-multiplexed asynchronous bus, similar to the C240x external interface. The external interface on the F2812 is mapped into five fixed zones shown in Figure 9-16.

Figure 9-16 shows the F2812 XINTF signals.

A. The mapping of XINTF Zone 7 is dependent on the XMP/ \overlineMC device input signal and the MP/ \overlineMC mode bit (bit 8 of XINTCNF2 register). Zones 0, 1, 2, and 6 are always enabled.

B. Each zone can be programmed with different wait states, setup and hold timing, and is supported by zone chip selects ( \overlineXZCS0AND1, \overlineXZCS2, \overlineXZCS6AND7), which toggle when an access to a particular zone is performed. These features enable glueless connection to many external memories and peripherals.

C. The chip selects for Zone 0 and Zone 1 are ANDed internally together to form one chip select ( \overlineXZCS0AND1). Any external memory that is connected to \overlineXZCS0AND1 is dually mapped to both Zone 0 and Zone 1.

D. The chip selects for Zone 6 and Zone 7 are ANDed internally together to form one chip select ( \overlineXZCS6AND7). Any external memory that is connected to \overlineXZCS6AND7 is dually mapped to both Zone 6 and Zone 7. This means that if Zone 7 is disabled (via the MP/ MC mode), then any external memory is still accessible via Zone 6 address space.

E. XCLKOUT is also pinned out on the F2810 and F2811 devices.

Figure 9-16. External Interface Block Diagram

Product Folder Links: TMS320F2810 TMS320F2810-Q1 TMS320F2811 TMS320F2811-Q1 TMS320F2812 TMS320F2812-Q1

The operation and timing of the external interface, can be controlled by the registers listed in Table 9-22.

Table 9-22. XINTF Configuration and Control Register Mappings

9.6.1 Timing Registers

XINTF signal timing can be tuned to match specific external device requirements such as setup and hold times to strobe signals for contention avoidance and maximizing bus efficiency. The XINTF timing parameters can be configured individually for each zone based on the requirements of the memory or peripheral accessed by that particular zone. This allows the programmer to maximize the efficiency of the bus on a per-zone basis. All XINTF timing values are with respect to XTIMCLK, which is equal to or one-half of the SYSCLKOUT rate, as shown in Figure 8-26.

For detailed information on the XINTF timing and configuration register bit fields, see the TMS320x281x DSP External Interface (XINTF) Reference Guide.

9.6.2 XREVISION Register

The XREVISION register contains a unique number to identify the particular version of XINTF used in the product. For the F2812, this register will be configured as described in Table 9-23.

Table 9-23. XREVISION Register Bit Definitions

9.7 Interrupts

Figure 9-17 shows how the various interrupt sources are multiplexed within the F281x devices.

A. Out of a possible 96 interrupts, 45 are currently used by peripherals.

Figure 9-17. Interrupt Sources

Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. On the F281x, 45 of these are used by peripherals as shown in Table 9-24.

The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.

When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the vector from INT2.1 and so forth.

TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1

TMS320F2812, TMS320F2812-Q1

Figure 9-18. Multiplexing of Interrupts Using the PIE Block

Table 9-24. PIE Peripheral Interrupts

(1) Out of the 96 possible interrupts, 45 interrupts are currently used. The remaining interrupts are reserved for future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR.

To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:

a. No peripheral within the group is asserting interrupts.

b. No peripheral interrupts are assigned to the group (example PIE group 12).

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Table 9-25. PIE Configuration and Control Registers

(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected.

9.7.1 External Interrupts

Table 9-26. External Interrupts Registers

Each external interrupt can be enabled/disabled or qualified using positive or negative going edge. For more information, see the TMS320x281x DSP System Control and Interrupts Reference Guide.

9.8 System Control

This section describes the F281x oscillator, PLL and clocking mechanisms, the watchdog function and the low-power modes. Figure 9-19 shows the various clock and reset domains in the F281x devices that will be discussed.

A. CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.

Figure 9-19. Clock and Reset Domains

TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1

TMS320F2812, TMS320F2812-Q1

The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 9-27.

Table 9-27. PLL, Clocking, Watchdog, and Low-Power Mode Registers

(1) All of the above registers can only be accessed by executing the EALLOW instruction.

(2) The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio) will not reset PLLCR.

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9.9 OSC and PLL Block

Figure 9-20 shows the OSC and PLL block on F281x.

Figure 9-20. OSC and PLL Block

The on-chip oscillator circuit enables a crystal to be attached to the F281x devices using the X1/XCLKIN and X2 pins. If a crystal is not used, then an external oscillator can be directly connected to the X1/XCLKIN pin and the X2 pin is left unconnected. The logic-high level in this case should not exceed VDD. The PLLCR bits [3:0] set the clocking ratio.

TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1

Table 9-28. PLLCR Register Bit Definitions

(1) The PLLCR register is reset to a known state by the XRS reset line. If a reset is issued by the debugger, the PLL clocking ratio is not changed.

9.9.1 Loss of Input Clock

In PLL enabled mode, if the input clock XCLKIN or the oscillator clock is removed or absent, the PLL will still issue a "limp-mode" clock. The limp-mode clock will continue to clock the CPU and peripherals at a typical frequency of 1–4 MHz. The PLLCR register should have been written to with a non-zero value for this feature to work.

Normally, when the input clocks are present, the watchdog counter will decrement to initiate a watchdog reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter will stop decrementing (that is, the watchdog counter does not change with the limp-mode clock). This condition could be used by the application firmware to detect the input clock failure and initiate necessary shut-down procedure for the system.

Note

Applications in which the correct CPU operating frequency is absolutely critical must implement a mechanism by which the DSP will be held in reset, should the input clocks ever fail. For example, an R-C circuit may be used to trigger the \overlineXRS pin of the DSP, should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would also help in detecting failure of the $V_{DD3VFL}$ rail.

TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1

9.10 PLL-Based Clock Module

The F281x has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 131072 XCLKIN cycles.

The PLL-based clock module provides two modes of operation:

• Crystal operation: This mode allows the use of an external crystal/resonator to provide the time base to the device.
• External clock source operation: This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external clock source input on the X1/XCLKIN pin.

A. TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will ensure start-up and stability over the entire operating range.

Figure 9-21. Recommended Crystal/Clock Connection

Table 9-29. Possible PLL Configuration Modes

9.11 External Reference Oscillator Clock Option

The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:

• Fundamental mode, parallel resonant
• $C_L$ (load capacitance) = 12 pF
• $C_{L1} = C_{L2} = 24$ pF
• $C_{shunt} = 6$ pF
• ESR range = 25 to 40 \Omega

9.12 Watchdog Block

The watchdog block on the F281x is identical to the one used on the 240x devices. The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog counter. Figure 9-22 shows the various functional blocks within the watchdog module.

Figure 9-22. Watchdog Module

The \overlineWDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer.

In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the watchdog. The WATCHDOG module will run off the PLL clock or the oscillator clock. The \overlineWDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 9.13, Low-Power Modes Block, for more details.

In IDLE mode, the \overlineWDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode.

In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence, so is the WATCHDOG.

9.13 Low-Power Modes Block

The low-power modes on F281x are similar to the 240x devices. Table 9-30 summarizes the various modes.

Table 9-30. Low-Power Modes

(1) The Exit column lists which signals or under what conditions the low-power mode will be exited. A low signal, on any of the signals, will exit the low-power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the IDLE mode will not be exited and the device will go back into the indicated low-power mode.

(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is still functional; while on the 24x/240x, the clock is turned off.

(3) On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.

The various low-power modes operate as follows:

IDLE Mode

This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.

STANDBY Mode

All other signals (including XNMI) will wake the device from STANDBY mode if selected by the LPMCR1 register. The user will need to select which signal(s) will wake the device. The selected signal(s) are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register.

HALT Mode

Only the XRS and XNMI external signals can wake the device from HALT mode. The XNMI input to the core has an enable/disable bit. Hence, it is safe to use the XNMI signal for this function.

Note

The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them when the IDLE instruction was executed.