Latest threads in Field-Programmable Gate Arrays

job offer fpga designer genova

we are looking for an fpga designer in Genova with the following knowledges: Operating systems Windows, Linux Programmi...

0 15yrs

rosaria.quadarella

0 15yrs rosaria.quadarella

Spartan3DSP TphDCM spec question

1) Why the spec calls out negative number for input holding time ? eg. TphDCM = - 0.26 ns 2) What does that means when...

9 15yrs

ccon67

9 15yrs ccon67

How do they handle shorts during the dynamic reconfiguration?

Normally, the tools check that there are no driver conflicts during synthesis and shut down all drivers when start the...

6 15yrs

do

6 15yrs do

small size SDSL modem

Hi all Can any one kindly tell me from where i can get small size (atleast width < 50mm) SDSL modem with ethernet input...

0 15yrs

bhatti.uzair

0 15yrs bhatti.uzair

Help with bidirectional interface of a FPGA with a uC

Hi need to implement a bidirectional 8 bit interface of a FPGA with a microcontroller. For now i am developing with a C...

4 15yrs

sink00

4 15yrs sink00

Ericsson Eurocom D1

Hi, I know this isn't the right place to ask this question, but since i use this forum frequently, i thought i should s...

0 15yrs

a1234573

0 15yrs a1234573

[ANNOUNCE] DSP-FPGA Programming Contest

DPStronics (http://www.dsptronics.com) is hosting a design contest (http://dsptronics.webfactional.com).

0 15yrs

techsupport

0 15yrs techsupport

What's the black and while round on FPGA slice?

Hi, I implemented a full combinatinal logic in Xilinx FPGA. A white and black eye appears on each SLICE. What does it m...

1 15yrs

eric.he

1 15yrs eric.he

Virtex 5 Rocket IO design for reading in ADC data.

Hello all, I am presently working with a virtix 5 FPGA and trying to get the rocket IOs to work with reading in the dat...

11 15yrs

john.kauffman

11 15yrs john.kauffman

JESD204A and Spartan-6 GTPs

Hi, I read the application note ?Virtex-5 FPGA Interface to JESD204A Compliant ADC?. I?m designing a pcb with a JESD204...

0 15yrs

y.hubert

0 15yrs y.hubert

Delta-Sigma in an FPGA

Hey all -- So I've got yet another project making me say "Gosh it'd be nice to be able to implement a DAC/ADC directly...

7 15yrs

rgaddi

7 15yrs rgaddi

XST 13.1 explodes with generic of enum type with only one member

It was all going so well until I asked XST to compile a VHDL entity with a generic of this type: type video_modes_e is...

13 15yrs

spam

13 15yrs spam

digitization of sensor array

Hi all I need to digitize a 32 channel sensor array, hosed in a pipe of 50mm diameter and 6m length. Sensors are hydrop...

3 15yrs

bhatti.uzair

3 15yrs bhatti.uzair

Depth of logical Circuit

Hi all, I sythesised (with Xilinx ISE) some complex logic circuit just consisting of AND and XOR gates and I am wonderi...

7 15yrs

sportfreund

7 15yrs sportfreund

P&R based on the post-map simulation model?

Hi, I need to modify the netlist generated from "Generate Post-map simulation model"(i.e. netgen). After the netlist mo...

3 15yrs

eric.he

3 15yrs eric.he

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