Delta-Sigma in an FPGA

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Hey all --

So I've got yet another project making me say "Gosh it'd be nice to be
able to implement a DAC/ADC directly in the FPGA."  And so I looked
around and found all the same white papers I always find wherein a
first-order delta-sigma modulated ADC or DAC is implemented using only
an FPGA and an RC filter.

I've done the DAC one before, but only in closed loop situations where
the actual accuracy doesn't matter much.  Has anyone actually tried
doing either of these in a real quantitative sense and gotten a feel for
what sorts of results can be accomplished?

Offhand, it seems like if you managed 12 bits it'd be a miracle.  Even
if you stabilized the power supply voltages (and had zero ground bounce
induced by the rest of the logic), it seems like you'd need rise/fall
symmetry into the femtoseconds on the digital outputs in order to not
shoot your linearity.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

Re: Delta-Sigma in an FPGA

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Or an LVDS line receiver

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Yep


LVDS helps here



Re: Delta-Sigma in an FPGA

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Wow -- I hadn't even thought about clock jitter.  I should have, but I
didn't.

I suppose if you _really_ wanted to do a hot-stuff job you'd take the
modulator output from the FPGA and regenerate it with a way-clean clock.  
You'll end up with delay in your loop, but lose some noise.

You'd have to sit back and do some math to figure out what sort of
performance could be hoped for from an any-old-which-way implementation.

--
Tim Wescott
Control system and signal processing consulting
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Re: Delta-Sigma in an FPGA
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And of course, as you start adding more external parts to the solution,
the advantages in board space and cost over just buying a chip vanish.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

Re: Delta-Sigma in an FPGA
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True.  But when you get right down to it, for an ADC just implementing
the necessary op-amp integrator and comparator is going to rival an
external ADC chip.

So maybe the thing to do is to figure out the best DAC that you can do
with FPGA only, and leave it at that...

--

Tim Wescott
Wescott Design Services
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Re: Delta-Sigma in an FPGA

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There is a paper which states that they can do 24 bit:

http://www.cse.cuhk.edu.hk/~phwl/mt/public/archives/papers/dac_fpt03.pdf

But I didn't found a description of the output stage. They measured -112
dB THD+N, but I don't think with all the noise on the supply voltages of
a FPGA that they drive a RC filter directly.

--
Frank Buss, http://www.frank-buss.de
piano and more:
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Re: Delta-Sigma in an FPGA
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God bless academics:

"In order to debug the system in a noise free environment, we used an
Agilent 16702B Logic analysis system to measure the output different
bit-width and order settings. The state mode sampling method is chosen
for synchronous sampling clocked by the FPGA board itself so that the
exact output of the DAC can be captured by the logic analyzer."

i.e. Measurements were taken to confirm that we get a stream of ones and
zeros that we can assume to be perfect rectangles framed by a perfect
clock.  One day, we hope to use this to generate an analog waveform that
we expect to have characteristics.

Can't imagine why I decided not to go for that PhD.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

Re: Delta-Sigma in an FPGA
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Yes, I love the -250dB noise floors on the plots, which (of course)
are simulated.

and real measurements, are entirely optional, 'we'll get to that
later'  !!

["An Audio Precision System Two Cascade audio analyzer with -112dB THD
+N for a 20kHz input will be used to further verify the system and
results will be presented at the conference."]

- but yes, in the real world, you can build 24b calibration DACs,
using an external element for the 1 bit DAC.

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