Field-Programmable Gate Arrays

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cheating Arria FPGA i/o count

Hi, I'm designing a pretty horrible board (33 page schematic!) that will use an Altera Arria II GX in the 572BGA packag...
19 comments posted 14yrs
posted by jjlarkin
19 comments posted 14yrs posted by jjlarkin

ISE and detecting flowthrus

Hi All, When doing multi-FPGA designs, what are some of the techniques that you use to detect if you have mistakenly pi...
2 comments posted 14yrs
posted by linuxfreak87
2 comments posted 14yrs posted by linuxfreak87

The smallest EDA tool

Robei is the world smallest EDA tool (less than 5Mbits) for Verilog based EDA software. It integrates modern graphical...
0 comments posted 14yrs
posted by micbot.com
0 comments posted 14yrs posted by micbot.com

meta assembler

Are there any commercially available meta assemblers like metalasm for programmable state machines in FPGAs? Thanks Dave
0 comments posted 14yrs
posted by dscolson
0 comments posted 14yrs posted by dscolson

Running Chipscope >=12.x on Linux.

When I tried to use Chipscope on my Linux machine, I got, the following error: COMMAND: open_cable INFO: Started ChipSc...
0 comments posted 14yrs
posted by wzab01
0 comments posted 14yrs posted by wzab01

Regarding virtex II pro xilinx XC2VP30 FF896

Sir I want to know how much voltage(min and max)to I/O connectors of J5 AND J6 in virtex II pro xilinx XC2VP30 FF896 bo...
1 comments posted 14yrs
posted by VARUN_AGR
1 comments posted 14yrs posted by VARUN_AGR

FPGA based PCIe Gen3 Endpoint question

I need to use the FPGA as PCIe Gen3 endpoint on one side and SPI ROM interface on the other side. Normally in x86 PC ar...
0 comments posted 14yrs
posted by cpandya
0 comments posted 14yrs posted by cpandya

vhdl:passing generic sized arrays to functions?

Im have different sizes of std_logic_vector arrays and want to run functions on different array types where vector size...
5 comments posted 14yrs
posted by mleikvol
5 comments posted 14yrs posted by mleikvol

[actel] resource usage by entity

Hi , I am currently designing a FPGA Actel Proasci3 and I would like to know the ressource usage (ram/flipflop...) for...
2 comments posted 14yrs
posted by alexis.gabin
2 comments posted 14yrs posted by alexis.gabin

MAXDELAY constraint

I have a 200 MHz clock gated by a BUFGMUX. I added some unrelated logic and the routing of the gate control signal got...
7 comments posted 14yrs
posted by ah
7 comments posted 14yrs posted by ah

VHDL Basic Question

I am new to VHDL and need some advice on connecting a vector array on an entity using a port map.I have an array of std...
12 comments posted 14yrs
posted by maxascent
12 comments posted 14yrs posted by maxascent

Testbench in verilog ps and human interactions don't mix

Hi all, I am testing a fairly slow design ( a IAMBIC keyer) and while I am dealing with slow signals (up to 120 WPM, ab...
3 comments posted 14yrs
posted by giuseppe.marullonospam
3 comments posted 14yrs posted by giuseppe.marullonospam

Altera Flex10K support ?

Hi I have found old parts lying around in the lab and I could put them to good use. Alas, they are not supported by Qua...
5 comments posted 14yrs
posted by nicolas.matringe
5 comments posted 14yrs posted by nicolas.matringe

extracting D from 1 / D*D

Hi Folks, Incredibly busy summer here, so before burning my brain cells, Googling or -worst- digging in my very dusty m...
13 comments posted 14yrs
posted by do_not_spam
13 comments posted 14yrs posted by do_not_spam