Hi ,
I am currently designing a FPGA Actel Proasci3 and I would like to know the ressource usage (ram/flipflop...) for each of module of the project , in Altera and Xilinx they report this information easily but I don't find it in Actel Designer (we also use synplify for synthesis so it shall be fine to use synplify reporting too)
Thank you for your tips!
Alexis
I was looking into exactly this today for something. By default, it seems to display the slowest few nets for each clock domain, and you can set somewhere how many to show. When I tried the GUI today I got a list of about 100.
You can right click somewhere and make a user defined "set" and go through and select a list of nets that you want to have in that set.. and it allows you to filter the search to find nets corresponding to a particular module.. you can filter it like *mymodule* to exclude everything else. When I did this it showed the delay information, but not everything else, I'm still trying to figure out how to get the rest (what I really want to know for the moment is minimum clock period). If/when I figure out the rest, I'll report back. Or maybe somebody else already knows this.
Steve
Ahh my bad. Right after I hit "send" I realized you are looking for resource usage, not timing information.
Well, synplify creates a file called your-design.srr, have you had a look at this file? It can end up be> I was looking into exactly this today for something.
Have something to add? Share your thoughts — no account required.
Ask the community — no account required