cheating Arria FPGA i/o count

Hi,

I'm designing a pretty horrible board (33 page schematic!) that will use an Altera Arria II GX in the 572BGA package. There are 240 pure I/O pins in this package, and 12 dedicated clock pins. I'm getting close to using up all the i/o pins, and starting to do silly things to save a pin here and there. Don't blame me, blame customer feature creep!

So, is it possible to use clock pins as general-purpose inputs? The documentation doesn't say so, but it does imply somewhere that clock nets can be used for non-clock functions like async resets, so there should be some not-too-disgusting way to used them as slow static inputs.

Pity they didn't dual-purpose the clock pins. It's not often you need

12 clocks.

Any thoughts/experience here?

Thanks

John

Reply to
John Larkin
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never used altera, but I'd think it is in here somewhere:

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-Lasse

Reply to
langwadt

"John Larkin" wrote in message news: snipped-for-privacy@4ax.com...

I don?t see why not, dedicated clocks mean that propagation time is minimized across the chip. But Quartus may balk at the idea. see

Some pins could be used as I/O , some can't.

Cheers

Reply to
Martin Riddle

Just did a test design using an Arria II GX and assigned an input pin to a dedicated clock input and it compiled OK.

Reply to
davew

If you're not sure, assign the pin and run the I/O Assignment Analysis. This validates all your I/O assignments without having to compile any code.

Reply to
davew

Cool! I'll have one of my FPGA guys try it, maybe on a real eval board (I don't drive the FPGA software myself.)

This very weekend, I'll assume it works and get on with my life.

Thanks

John

Reply to
John Larkin

It does mean the I/O assignment meets the chip's specs, which is all that was asked.

Reply to
krw

Just because a program compiles does not mean it will work...

Reply to
Robert Baer

Does PS boot mode save a pin or two ?..

Reply to
TTman

For Altera Cyclone X, you can use clock-inputs as general-purpose inputs with some restrictions, most important:

- No internal pullups possible

- No fast I/O-register

It is not possible to use them as output.

I guess, the same applies also for the Arria-parts, but I have not double-checked.

Regards,

Thomas

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Reply to
Thomas Entner

It's not Xilinx, it's Altera.

Reply to
scrts

I think the people at comp.arch.fpga might be more experienced at this.

Werner

Reply to
Werner

We're doing that already... a mere 29 million bits!

John

Reply to
John Larkin

The Arria GZ parts say specifically that clock pins can be I/Os. It's not clear on the GX if they can be inputs. We're using the A2 45GX.

My schematic names signals like

SIG3_F for FPGA i/o SIG4_FS serdes SIG5_FD special/dedicated SIG6_FI FPGA input, i/o or (maybe) clock pin

and I let The Brat (our layout person) pick whichever FPGA pins that route best. There's an ARM processor with similar rules, SIG5_U etc.

John

Reply to
John Larkin

Ohhh, that was mean. True, but mean.

John

Reply to
John Larkin

Right. I did crosspost there.

John

Reply to
John Larkin

Even Xilinx will tell you about illegal I/O assignments.

Reply to
krw

Are you using I/O banking? I tend to code such things into the schematic symbol, rather than signal names. Also, be careful if you use external RAM I/O macros. Some of these are picky about I/O assignments.

Reply to
krw

All the banks are 3.3 volts, and no DRAM, so any i/o pin is as good as any other. The main clock is a mere 125 MHz.

The schematic symbol for the FPGA is in fact a bunch of separate blocks, "gates" to PADS: a couple for PCIe, one for each i/o bank, one for core power, one for ground, one for config. Each bank block has its own Vccio pins.

We are doing PCI Express, but those pins are hard dedicated, so I can assign off-pages to the specific FPGA pins involved, locking them down, and preplan the routing for those.

John

Reply to
John Larkin

Sure, I do the same, except I'll break things down into functional blocks rather than just along bank boundaries. I never reuse symbols for FPGAs. You can still code the pin-swapping information into the pin names.

Sure, name them with their function and I/O pin number and mark them as non-swappable. Again, there is no need to identify these pins by their signal names. Doesn't hurt, just adds more mess to the naming convention.

Reply to
krw

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