cheating Arria FPGA i/o count

never used altera, but I'd think it is in here somewhere:

-Lasse

"John Larkin" wrote in message news: snipped-for-privacy@4ax.com...

I don?t see why not, dedicated clocks mean that propagation time is minimized across the chip. But Quartus may balk at the idea. see

Some pins could be used as I/O , some can't.

Cheers

Just did a test design using an Arria II GX and assigned an input pin to a dedicated clock input and it compiled OK.

If you're not sure, assign the pin and run the I/O Assignment Analysis. This validates all your I/O assignments without having to compile any code.

Cool! I'll have one of my FPGA guys try it, maybe on a real eval board (I don't drive the FPGA software myself.)

This very weekend, I'll assume it works and get on with my life.

Thanks

John

It does mean the I/O assignment meets the chip's specs, which is all that was asked.

Just because a program compiles does not mean it will work...

Does PS boot mode save a pin or two ?..

For Altera Cyclone X, you can use clock-inputs as general-purpose inputs with some restrictions, most important:

- No internal pullups possible

- No fast I/O-register

It is not possible to use them as output.

I guess, the same applies also for the Arria-parts, but I have not double-checked.

Regards,

Thomas

It's not Xilinx, it's Altera.

I think the people at comp.arch.fpga might be more experienced at this.

Werner

We're doing that already... a mere 29 million bits!

John

The Arria GZ parts say specifically that clock pins can be I/Os. It's not clear on the GX if they can be inputs. We're using the A2 45GX.

My schematic names signals like

SIG3_F for FPGA i/o SIG4_FS serdes SIG5_FD special/dedicated SIG6_FI FPGA input, i/o or (maybe) clock pin

and I let The Brat (our layout person) pick whichever FPGA pins that route best. There's an ARM processor with similar rules, SIG5_U etc.

John

Ohhh, that was mean. True, but mean.

John

Right. I did crosspost there.

John

Even Xilinx will tell you about illegal I/O assignments.

Are you using I/O banking? I tend to code such things into the schematic symbol, rather than signal names. Also, be careful if you use external RAM I/O macros. Some of these are picky about I/O assignments.

All the banks are 3.3 volts, and no DRAM, so any i/o pin is as good as any other. The main clock is a mere 125 MHz.

The schematic symbol for the FPGA is in fact a bunch of separate blocks, "gates" to PADS: a couple for PCIe, one for each i/o bank, one for core power, one for ground, one for config. Each bank block has its own Vccio pins.

We are doing PCI Express, but those pins are hard dedicated, so I can assign off-pages to the specific FPGA pins involved, locking them down, and preplan the routing for those.

John

Sure, I do the same, except I'll break things down into functional blocks rather than just along bank boundaries. I never reuse symbols for FPGAs. You can still code the pin-swapping information into the pin names.

Sure, name them with their function and I/O pin number and mark them as non-swappable. Again, there is no need to identify these pins by their signal names. Doesn't hurt, just adds more mess to the naming convention.