Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15253 Threads Posts
to

Xilinx SP605 DDR3 Allegro 15.7 Viewer Questions

I am designing a Spartan-6 pcb with DDR3 by way of Memory Control Block and with various video interfaces. Before I sta...
5 comments posted 14yrs
posted by bradsmallridge
5 comments posted 14yrs posted by bradsmallridge

Browser-Based Timing Diagram Editor

I used to use a really nice, simple, browser-based timing diagram editor, and now I've forgotten the name and URL of th...
2 comments posted 14yrs
posted by kevin.neilson
2 comments posted 14yrs posted by kevin.neilson

gigabit ethernet problem

Hi, I am using xilinx spartan3 xc3s4000 in my design. It is interfaced with 2 national Gigabit PHYs. So i receive a pac...
16 comments posted 14yrs
posted by a1234573
16 comments posted 14yrs posted by a1234573

Xilinx Spartan-3 Starter Kit and Webpack 13.2

Hello all, I'm just starting into FPGA's, and have access to a Spartan-3 Starter board. Even though it dates back to 20...
2 comments posted 14yrs
posted by alekceywk
2 comments posted 14yrs posted by alekceywk

SIM card 1.8V / 3V sensing

Can anyone steer me in the right direction of an article how one is meant to determine if a SIM card is of the 1.8V, or...
2 comments posted 14yrs
posted by spam
2 comments posted 14yrs posted by spam

How to digitize the VGA output using FPGA?

I would like to know if there is a development kit and documentation available to digitize the VGA siganls to create th...
5 comments posted 14yrs
posted by cpandya
5 comments posted 14yrs posted by cpandya

Registers at I/O

Synthesis optimization people seem to like registers at I/O. Particularly, in Xilinx manual: "The synthesis tools will...
7 comments posted 14yrs
posted by do
7 comments posted 14yrs posted by do

Virtex 6 dev. board suppliers?

Hi, I'm looking for a Xilinx Virtex 6 based dev. board, (with PCIe and SFP connectors for 10G Ethernet). Other than Hit...
6 comments posted 14yrs
posted by rupertlssmith
6 comments posted 14yrs posted by rupertlssmith

LFSR in xilinx 13.2

Hi, I am using xilinx 13.2 for my design synthesis and i want to use xilinx IP for LFSR but i cannot find it in core ge...
4 comments posted 14yrs
posted by a1234573
4 comments posted 14yrs posted by a1234573

clock enable for fixed interval

What would be the proper way to clock a register at a fixed multiple of the system clock? I am trying to create a signa...
7 comments posted 14yrs
posted by james.knoll
7 comments posted 14yrs posted by james.knoll

CONSTRAINTS

Sir When we run our vhdl programme it sysnthesize and implemented witout any error, In place and route report it gives...
1 comments posted 14yrs
posted by VARUN_AGR
1 comments posted 14yrs posted by VARUN_AGR

Has anybody used IOB_DLY_ADJ with S(2:0) input?

Hi, I have a DDR input which every now and then gives me a nonfunctional implem= entation due to unlucky input data clo...
1 comments posted 14yrs
posted by svenn.bjerkem
1 comments posted 14yrs posted by svenn.bjerkem