I am designing a Spartan-6 pcb with DDR3 by way of Memory Control Block and with various video interfaces. Before I start with my own design, I thought I would look at other available designs, including the Xilinx SP605 design. I downloaded the design files and opened file 4199_SP605_brd_091909.brd with Allegro's Summer '09 viewer, that is, v15.7. There are top, bottom, and four inner signal layers that are nicely viewable by manipulating the display enables and colors. You can click on the info button to get net information, a clear advantage over Gerber files. I'll post some questions about the routes on these signal layers later but now I have a question about the inner power plane layers.
These inner plane layers display as completely filled areas with no regard to vias. All the vias appear to connect to the planes whereas it's clear that a high proportion of vias should not. Now I'm an old EAGLE user and I remember that I had to click on the ratnest tool in order to get the polygon fills to "render". But I don't see any comparable button on the Allegro Free Viewer. Is it possible to get these via connections to show properly?
Another issue is the plot. I can plot to my printer, that's good. But when I plot to a file, the file has a .PLT extension. I've already tried TotalCADConverter to get this into another form, a .BMP file, which did not work. All I got was one long line. Has any one converted these .PLT files successfully with free software?
Thanks in advance,
Brad Smallridge Ai Vision