Hi All, I'm a relatively newbe of FPGA development. We are working on a design involving BFSK modulator / demodulator pair. We are usign the built-in FIFO18 component of Xilinx for Virtex5. For some reason the fifo output seems to be NOT proper. Could any of you suggest a way to investigate this, maybe using chipscope? I tried to connect the Data output of the fiso to an ILA driven by read clock but the clock is much faster than the read enable signal so I see a lot of samples of the same value.
Any adie about hot to do?
Thanks a lot in advance
Best regards
Fabio Giovagnini Aurion s.r.l. Bologna (Italy)
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