'x' state on one bit of the input bus of an adder cause the output bus be all 'x' during simulation

The "timing" simulation is probably on a post synthesis or post fit netlist= , where the "+" has been converted to a proper adder in whatever logic is a= ppropriate for your application. Describe a complete adder out of plain gat= es and you will get what you want. (i.e. describe a ripple-carry adder or s= ome other architecture)

Moreover, why do you care about the details of the output of an adder with = an X input?

Chris

h an X input?

Because the actual behavior of the HW is implementation dependent, the RTL operator does not attempt to define its behavior for inputs containing meta-values, beyond the whole result being 'unknown'.

To compare the results, I would take the RTL outputs, run them through a 'X' to '-' ('unknown' to 'dont care') conversion (probably need to write your own function), and then use std_match() to compare the RTL vs gate level outputs.

This in effect says that for verification, if the output of the RTL is not known, then the output of the gate level sim is of no consequence.

Andy

It takes some bit manipulation to handle unknowns exactly. That takes programmer time and CPU time (I've done it). Most likely they traded off exactness for speed. Usually, you don?t care about the result unless it is totally defined. As someone else suggested, you might need to write your own model if you want exactness.

Gary

I have an adder: module adder( input [1:0] add1, input [1:0] add2, output [2:0] addout ); assign addout = add1 + add2; endmodule

The input is: add1 = 2'bx0; add2 = 2'b00;

The RTL simulation result is: addout = 3'bxxx;

The Timing simulation result is: addout = 3'b0x0; and this is what I expected.

How can I solve the mismatch in RTL simulation?