I have an adder: module adder( input [1:0] add1, input [1:0] add2, output [2:0] addout ); assign addout = add1 + add2; endmodule
The input is: add1 = 2'bx0; add2 = 2'b00;
The RTL simulation result is: addout = 3'bxxx;
The Timing simulation result is: addout = 3'b0x0; and this is what I expected.
How can I solve the mismatch in RTL simulation?