Field-Programmable Gate Arrays

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how to debug a C/C++ application in NIOS II IDE

hi all, how to debug a C/C++ application in NIOS II IDE?? what r the instructins/funtions used for programming a LED usi...
0 comments posted 21yrs
posted by sankalp.singhal
0 comments posted 21yrs posted by sankalp.singhal

Actel Designer on Linux

Does anyone have any experience of running Actel Designer on Linux? We currently use WinXP, and have recently been info...
3 comments posted 21yrs
posted by neilla
3 comments posted 21yrs posted by neilla

How many logic cells are there in one slice

hi all, i wud like to know how many logic cells are there in 1 slice. 1 slice contains 2 LUTs. OK to tell in particular...
5 comments posted 21yrs
posted by Puneetsingh81
5 comments posted 21yrs posted by Puneetsingh81

XPS: Create/Import File structure

I am trying to use a 3rd party IP core I2S_OPB as a peripheral in my microblaze hw design. When using the Create/Import...
0 comments posted 21yrs
posted by Kjacek
0 comments posted 21yrs posted by Kjacek

Problems with Constraints (Xilinx, ISE 6.3)

So I've got the whole VHDL thing down, but I've still got some problems understanding how to set up timing constraints....
4 comments posted 21yrs
posted by rgaddi
4 comments posted 21yrs posted by rgaddi

DDR2 based Xilinx Development boards ?

Can anybody recommend a decent DDR2 development board with a Xilinx FPGA ? I have the TED board here and that seems to...
1 comments posted 21yrs
posted by russelmann
1 comments posted 21yrs posted by russelmann

Q, BRAM initializing using INIT_0X

Hi I have consulted the following link to initialize BRAM. http://www.fpga-faq.org/FAQ_Pa=ADges/0031_How_to_initialize_...
1 comments posted 21yrs
posted by pasacco
1 comments posted 21yrs posted by pasacco

For accessing my SDRAM,what should i do?

I try to access the SDRAM in my program, and wait for enough time before writing data to SDRAM,but i find the value of S...
8 comments posted 21yrs
posted by mlpei279
8 comments posted 21yrs posted by mlpei279

Linux on Xilinx ml310

Hallo, i try to install debian (woody) for ppc on the xilinx ml310, but without success. It seems that the powerpc buil...
1 comments posted 21yrs
posted by henning
1 comments posted 21yrs posted by henning

CORDIC bit-serial vs. bit-parallel

Hello, I'm trying to write a CORDIC macro for a polar transmitter FPGA design. I've used the parallel approach, but whe...
5 comments posted 21yrs
posted by m_oylulan
5 comments posted 21yrs posted by m_oylulan

Xilinx IP: PCI Express

Hi, we recently bought the PCI Express Endpoint Core from Xilinx and implemented it into a Virtex 2 Pro 50 device. We h...
2 comments posted 21yrs
posted by fpgahardware
2 comments posted 21yrs posted by fpgahardware

Detaching the schematic viewer under ISE Webpack

Just wondering if it is possible to detach the schematic viewer from the main ise window. (in 7.1i or so.) Also is it p...
3 comments posted 21yrs
posted by georgevarughese
3 comments posted 21yrs posted by georgevarughese