Latest threads in Field-Programmable Gate Arrays

Actel Designer on Linux

Does anyone have any experience of running Actel Designer on Linux? We currently use WinXP, and have recently been info...

3 21yrs

neilla

3 21yrs neilla

Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE

hi group, I have just started using NIOS II with Quartus II ver 4.2 ..I tried a simple project having a NIOS CPU, an on...

8 21yrs

sankalp.singhal

8 21yrs sankalp.singhal

How many logic cells are there in one slice

hi all, i wud like to know how many logic cells are there in 1 slice. 1 slice contains 2 LUTs. OK to tell in particular...

5 21yrs

Puneetsingh81

5 21yrs Puneetsingh81

Why do VHDL gate level models simulate slower than verilog

Hi Group, Iam not sure if this is the right group to post my query on,butI would appreciate any kind of information.I a...

3 21yrs

abilashreddy

3 21yrs abilashreddy

where are the PAO files for the system.bsp stored???

Hi all I ahve a question to ask the public using EDK windows version. Suppos I create a BSP, where are the pao files st...

0 21yrs

nara_chak45

0 21yrs nara_chak45

XPS: Create/Import File structure

I am trying to use a 3rd party IP core I2S_OPB as a peripheral in my microblaze hw design. When using the Create/Import...

0 21yrs

Kjacek

0 21yrs Kjacek

Problems with Constraints (Xilinx, ISE 6.3)

So I've got the whole VHDL thing down, but I've still got some problems understanding how to set up timing constraints....

4 21yrs

rgaddi

4 21yrs rgaddi

DDR2 based Xilinx Development boards ?

Can anybody recommend a decent DDR2 development board with a Xilinx FPGA ? I have the TED board here and that seems to...

1 21yrs

russelmann

1 21yrs russelmann

Q, BRAM initializing using INIT_0X

Hi I have consulted the following link to initialize BRAM. http://www.fpga-faq.org/FAQ_Pa=ADges/0031_How_to_initialize_...

1 21yrs

pasacco

1 21yrs pasacco

For accessing my SDRAM,what should i do?

I try to access the SDRAM in my program, and wait for enough time before writing data to SDRAM,but i find the value of S...

8 21yrs

mlpei279

8 21yrs mlpei279

Linux on Xilinx ml310

Hallo, i try to install debian (woody) for ppc on the xilinx ml310, but without success. It seems that the powerpc buil...

1 21yrs

henning

1 21yrs henning

CORDIC bit-serial vs. bit-parallel

Hello, I'm trying to write a CORDIC macro for a polar transmitter FPGA design. I've used the parallel approach, but whe...

5 21yrs

m_oylulan

5 21yrs m_oylulan

Xilinx IP: PCI Express

Hi, we recently bought the PCI Express Endpoint Core from Xilinx and implemented it into a Virtex 2 Pro 50 device. We h...

2 21yrs

fpgahardware

2 21yrs fpgahardware

Detaching the schematic viewer under ISE Webpack

Just wondering if it is possible to detach the schematic viewer from the main ise window. (in 7.1i or so.) Also is it p...

3 21yrs

georgevarughese

3 21yrs georgevarughese

VHDL array question

Hi there, I'm having a bit of confusion using arrays in VHDL. I know I can: type heap is array (0 to 800) of std_logic;...

6 21yrs

randomdude

6 21yrs randomdude

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