Field-Programmable Gate Arrays

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VHDL array question

Hi there, I'm having a bit of confusion using arrays in VHDL. I know I can: type heap is array (0 to 800) of std_logic;...
6 comments posted 21yrs
posted by randomdude
6 comments posted 21yrs posted by randomdude

About back annotated simulations...

...what are their really use for ? For several years, I developped and succesfully used FPGA(Xilinx, Altera, Actel) des...
10 comments posted 21yrs
posted by fcez05
10 comments posted 21yrs posted by fcez05

Which Simulators

I'm sure this kind of things has come up in the past, but given that things change, I'd like to throw this out there. W...
7 comments posted 21yrs
posted by arlencox
7 comments posted 21yrs posted by arlencox

Jam Byte-Code Player for 8051

Hallo all, I'm trying to implement Jam Byte-Code player using the source code(8051 Jam byte code player) provided by Al...
7 comments posted 21yrs
posted by user100
7 comments posted 21yrs posted by user100

Virtex 4 MGTVREF pin reference circuit

There is a reference circuit for the MGTVREF pin on page 132 of the Virtex-4 RocketIO MGT User Guide. There is a resist...
0 comments posted 21yrs
posted by jason.stubbs
0 comments posted 21yrs posted by jason.stubbs

Virtex-2 JTAG problem

I'm trying to get a new board up and running, and the first order of business is trying to program a Virtex-2 and two X...
6 comments posted 21yrs
posted by
6 comments posted 21yrs posted by

delays

Hello all, i am using the Spartan 3 (XC3s200). I have a clock signal coming into my FPGA expansion port and all i want...
5 comments posted 21yrs
posted by amir.intisar
5 comments posted 21yrs posted by amir.intisar

Registers replication on Xilinx IOBs

Dear all, when synthesizing my design with XST, i get some messages like this one; "Flip-flop ... has been replicated 1...
4 comments posted 21yrs
posted by giachella.g
4 comments posted 21yrs posted by giachella.g

Silicon Valley FPGA position

FPGA Engineer Necessary Skills =B7 Responsible for implementing DSP functional block in FPGA from conception through HD...
2 comments posted 21yrs
posted by headlandsconsulting
2 comments posted 21yrs posted by headlandsconsulting

Altera Apex20KE PLL output jitter problem

Hello I have a design based on an Apex20K400E which uses the AltClockBoost to generate a 48MHz output clock from a 60MH...
5 comments posted 21yrs
posted by nic_o_mat
5 comments posted 21yrs posted by nic_o_mat

why is it wrong with "sin"?

Hi all, I cann't do the math problems, such as: sin, cos... Our condition is as follows: At president, we are doing som...
2 comments posted 21yrs
posted by lnzhao
2 comments posted 21yrs posted by lnzhao