Field-Programmable Gate Arrays

FPGA implementation of Interpolation controller for a Timing Recovery Loop

Hi All, I'm looking at FPGA implementation of Timing Recovery Loop and Interpolatio n controller. I would like to refer...

0 comments posted 13yrs

posted by dinukaudesh

0 comments posted 13yrs posted by dinukaudesh

Modelsim ought to be cheaper

Why is Modelsim so expensive? It is a mature product and yet it segfaults on me all the time. Constantly. Often, when i...

19 comments posted 13yrs

posted by kevin.neilson

19 comments posted 13yrs posted by kevin.neilson

Inferring Xilinx BlockRAM FIFO

The Xilinx built-in blockRAM FIFOs seem pretty nice, but is there any way t o infer them? Probably not. They're not tha...

3 comments posted 13yrs

posted by kevin.neilson

3 comments posted 13yrs posted by kevin.neilson

CFP - High-level Synthesis - Methodologies and Practice

========================= ========================= =============== Hindawi VLSI Design Special issue on High-level syn...

0 comments posted 13yrs

posted by nikolaos.kavvadias

0 comments posted 13yrs posted by nikolaos.kavvadias

FPGA board with 4 channel 500Msps ADC?

Hi, I'm looking for possibly cheap FPGA based board with 4 channel 500 Msps ADC (at least 8bit). The board should allow...

5 comments posted 13yrs

posted by wzab01

5 comments posted 13yrs posted by wzab01

Catapult C floating point exp() function?

Hello all, I was wondering if catapult C HLS has a built in exp() for floating point numbers. If yes is the generated R...

5 comments posted 13yrs

posted by turin231

5 comments posted 13yrs posted by turin231

XILINX Artix-7

Hallo, hat jemand Erfahrungen mit der neuen 7-er Serie von XILINX, speziell mit dem Artix-7? Hat schon jemand Erfahrunge...

1 comments posted 13yrs

posted by bodo_rauhut

1 comments posted 13yrs posted by bodo_rauhut

Programming the old Spartan S3E Sample Board

Folks, I bought a couple of these on Ebay as they were cheap but I am having fun trying to program them. The program is...

1 comments posted 13yrs

posted by dave.g4ugm

1 comments posted 13yrs posted by dave.g4ugm

FPGA for large HDMI switch

I am working on a project that will involve a large HDMI switch - up to 16 inputs and 16 outputs. We haven't yet decide...

15 comments posted 13yrs

posted by david

15 comments posted 13yrs posted by david

ISIM issue with 'last_value attribute in functions

In the following forum thread, member Alex reports some odd behavior when using ISIM to simulate some code that is part...

0 comments posted 13yrs

posted by urb

0 comments posted 13yrs posted by urb

MISC - Stack Based vs. Register Based

I have been working with stack based MISC designs in FPGAs for some years. All along I have been comparing my work to t...

60 comments posted 13yrs

posted by gnuarm

60 comments posted 13yrs posted by gnuarm

xcv800 free design tools

HI I have an old Xilinx board called "XCV800" .So my question is: What is the xilinx software version that supports the...

1 comments posted 13yrs

posted by loveimmigr

1 comments posted 13yrs posted by loveimmigr

What a Xilinx fpga could do in 1988

I'm writing up a project that ran from 1988 to 1991. It involved building an ECL-based digital processor that ran at 25...

10 comments posted 13yrs

posted by bill.sloman

10 comments posted 13yrs posted by bill.sloman

Xilinx tools for XC3020???

I've got a 20-year-old Xilinx XC3020 development board. I think it would be fun to fire it up and bring it to the 20th...

14 comments posted 13yrs

posted by mbuttspdx

14 comments posted 13yrs posted by mbuttspdx

pullup in Xilinx ISE 10.1

I tried building a small project in ISE 10.1 using the CoolRunner II CPLD XC2C128 and ran into a problem with pullups....

2 comments posted 13yrs

posted by elson

2 comments posted 13yrs posted by elson