Field-Programmable Gate Arrays

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How to Use Spartan 6 Ethernet Port

Hi all I need your help.I met a problem when I use the SPARTAN-6 FPGA board (xc6slx45-csg324c).I'm currently working on...
0 comments posted 13yrs
posted by zinabuhaile26
0 comments posted 13yrs posted by zinabuhaile26

Problems with Spartan6 CRC calculation

I am unsuccessfully trying to update Spartan6 CRC checksums after I make packet modifications. This is not a problem fo...
2 comments posted 13yrs
posted by neil.steiner
2 comments posted 13yrs posted by neil.steiner

USB Download Cable for Lattice Devices

I am looking to incorporate the download capability for the Lattice USB download cable into a design. I found an app no...
4 comments posted 13yrs
posted by gnuarm
4 comments posted 13yrs posted by gnuarm

FPGA Exchange

I'd like to introduce a new FPGA discussion forum. It's called FPGA Exchange, and you can check it out at: http://fpga-...
14 comments posted 13yrs
posted by Guy.Eschemann
14 comments posted 13yrs posted by Guy.Eschemann

Pure HDL Xilinx Zynq Arm Instantiation

Hello All, I have a Xilinx Zynq development board and I am starting to teach myself to build systems for Zynq. The reco...
6 comments posted 13yrs
posted by padudle
6 comments posted 13yrs posted by padudle

Equivalent .tdf file in Aldec Active-HDL?

Is there an equivalent .tdf file in Aldec Active-HDL? One can find "text design file" in Quartus II. I like the same in...
0 comments posted 13yrs
posted by rc0clx
0 comments posted 13yrs posted by rc0clx

comparing between Xilinx and altera

I have a project that need about 300KLE, I want to choose a device between the Xilinx V7 and Altera Stratix5, please gi...
2 comments posted 13yrs
posted by bjzhangwn
2 comments posted 13yrs posted by bjzhangwn

Chasing Bugs in the Fog

I have a bug in a test fixture that is FPGA based. I had thought it was in the software which controls it, but after ma...
9 comments posted 13yrs
posted by gnuarm
9 comments posted 13yrs posted by gnuarm

HBA tomorrow (Friday) 14th June

Hi Friday people, I won't be in on Friday - but Darren P. has kindly agreed to open up and operate Request Line. See you...
4 comments posted 13yrs
posted by apf
4 comments posted 13yrs posted by apf

DDR2 Concurrent Auto Precharge

I have come across a VHDL Free Model Foundry mt47h16m16.vhd which gives me some errors. Has anyone else used this model...
5 comments posted 13yrs
posted by spam
5 comments posted 13yrs posted by spam

[ANN] LOOPGEN-Fast hardware looping VHDL IPs

The LOOPGEN IP collection provides fast hardware architectures for implementing nested loop structures. The collection...
0 comments posted 13yrs
posted by nikolaos.kavvadias
0 comments posted 13yrs posted by nikolaos.kavvadias

New soft processor core paper publisher?

I have a general purpose soft processor core that I developed in verilog. The processor is unusual in that it uses four...
219 comments posted 13yrs
posted by tammie.eric
219 comments posted 13yrs posted by tammie.eric