Field-Programmable Gate Arrays

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Mentor Graphics Precision RTL + LatticeECP3 Versa

Could I use the Precision RTL with the LatticeECP3 Versa development kit? LatticeSemi does provide a one year evaluatio...
1 comments posted 13yrs
posted by rc0clx
1 comments posted 13yrs posted by rc0clx

[ANN] XMODZ-Fast modulo reduction VHDL IPs

The XMODZ IP collection provides fast hardware implementations for the modulo computation on integers. The collection c...
5 comments posted 13yrs
posted by nikolaos.kavvadias
5 comments posted 13yrs posted by nikolaos.kavvadias

openCv and NiosII IDE

hi, Can I link libraries to a project using the Nios II IDE tools? I am using v9.0 and I want to link the OpenCV librar...
0 comments posted 13yrs
posted by 95229
0 comments posted 13yrs posted by 95229

FPGA Board : Indirect SPI not working

I was able to make my own custom FPGA shield for an ARM Cortex M3 board (ar duino footprint ofcourse!). I used the Papi...
0 comments posted 13yrs
posted by shanjitsingh
0 comments posted 13yrs posted by shanjitsingh

Cubic Spline Interpolator

This isn't a question; I'm putting this here as a reference so I can find i t in the future. This is how to build a cub...
5 comments posted 13yrs
posted by kevin.neilson
5 comments posted 13yrs posted by kevin.neilson

Die size of BRAM/DSP48 in CLBs

Does anybody know how big a BRAM or DSP48 is in terms of CLBs? (In a Virtex 5/6/7 part.) I was wondering, in terms of d...
5 comments posted 13yrs
posted by kevin.neilson
5 comments posted 13yrs posted by kevin.neilson

XILINX Artix-7 DDR2-RAM-Controller

Hello, I'm trying to implement a DDR2-RAM-Controller for the ARTIX-7 FPGA and I have some "problems" during generation...
5 comments posted 13yrs
posted by bodo_rauhut
5 comments posted 13yrs posted by bodo_rauhut

Linting tool setup

Greetings all, Further to previous thread(s), has anyone here experience in setting up a linting tool such as Spyglass...
5 comments posted 13yrs
posted by 2161
5 comments posted 13yrs posted by 2161

Xilinx SDK 14.5 debug

I have a Microblaze design in SDK that I am trying to debug. I have an IP block with some registers that I can read and...
0 comments posted 13yrs
posted by 4575
0 comments posted 13yrs posted by 4575

The UK Device Developers' Conference - Last call

Hi, http://www.device-developer-conference.co.uk Just a final call, to say that we have a few places still available at...
0 comments posted 13yrs
posted by 9917
0 comments posted 13yrs posted by 9917

Any experience of Equivalence Checking tools?

Greetings all, Has anyone hereabouts any experience with the use of Equivalence Checking tools in an FPGA context, for...
2 comments posted 13yrs
posted by 2161
2 comments posted 13yrs posted by 2161

DEP function development on a low budget

Is it at all practical for home-builders on a very limited budget to develop DSP type functions, such as filters and th...
5 comments posted 13yrs
posted by bv
5 comments posted 13yrs posted by bv

FPGA Development Board with hard PowerPC

I am working on a channel emulator which is based on a FPGA development board and a custom based RF board connected to...
3 comments posted 13yrs
posted by 94991
3 comments posted 13yrs posted by 94991

Low cost and/or small size CPU in an FPGA

What is the lowest cost and/or the smallest CPU in an FPGA. Can a CPU with reasonable code space fit into a 44 pin FPGA...
9 comments posted 13yrs
posted by hamilton
9 comments posted 13yrs posted by hamilton