I have a bug in a test fixture that is FPGA based. I had thought it was in the software which controls it, but after many hours of chasing it around I've concluded it must be in the FPGA code.
I didn't think it was in the VHDL because it had been simulated well and the nature of the bug is an occasional dropped character on the receive side. Who can't design a UART? Well, it could be in the handshake with the state machine, but still...
So I finally got around to adding some debug signals which I would monitor on an analyzer and guess what, the bug is gone! I *hate* when that happens. I can change the code so the debug signals only appear when a control register is set to enable them, but still, I don't like this. I want to know what is causing this DURN THING!
Anyone see this happen to them before?
Oh yeah, someone in another thread (that I can't find, likely because I don't recall the group I posted it in) suggested I add synchronizing FFs to the serial data in. Sure enough I had forgotten to do that. Maybe that was the fix... of course! It wasn't metastability, I bet it was feeding multiple bits of the state machine! Durn, I never make that sort of error. Thanks to whoever it was that suggested the obvious that I had forgotten.