Verilog: "don't care" in

I'd just code the easy things. Since you know it's modulo-4 then just mask (or ignore) the lower two-bits. If you mean that inputs > 19 never occur, then mask (or ignore) bits over bit 4.

Anything else usually isn't worth the effort. If there's any way the synthesis tool can figure out this extra information, it'll do very good job at optimizing it on it's own.

My 2 cents...

--Mark

Hi,

thanks for the reply. Agree, I don't want to get stuck in micro-optimization. I was just hoping for a simple solution like

// synthesis assume(value < 20)

(this is FAKE. I've made it up. Don't use it)

Theoretically, the synthesis tool could figure it out, but I doubt it's that smart.

BTW, a mistake in my post: I meant modulo-20 (not 4). The _increment_ in my example is 4, and the only cases that trigger the condition are

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Synplify performs reachability analysis on counters and state machines. With that information, it will optimize comparisons to the count or state. Whether it can determine that some values are not reachable, I cannot tell from the information given.

Andy