Field-Programmable Gate Arrays

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Xilinx PCIe core vs. Icarus Verilog

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Does anybody know if the Xilinx PCI Express cores from Xilinx can run w/...
2 comments posted 20yrs
posted by spamtrap
2 comments posted 20yrs posted by spamtrap

For those looking for the Spartan3E starter board...

The Xilinx Online Store just started showing "In Stock" availability for all 4 power-optioned Spartan3E Starter Kit boar...
0 comments posted 20yrs
posted by johnhandwork
0 comments posted 20yrs posted by johnhandwork

Synthesizer is creating unwanted global resources

Hello all, I was experimenting a design with V4 lx60. Synthesizer is synplify 8.0 and xilinx ISE7.1 for PAR. Two clocks...
8 comments posted 20yrs
posted by vssumesh_asic
8 comments posted 20yrs posted by vssumesh_asic

Xilinx OPB Arbiter

Hello, I'm currently building a system with one microblaze and two masters opb component, But in order to set up priori...
0 comments posted 20yrs
posted by imp.chris
0 comments posted 20yrs posted by imp.chris

OPB_SPI timing problems

Hello, I have a microblaze system containing an OPB_SPI core. It used to work without adding special timing constraints...
0 comments posted 20yrs
posted by Karel.Deprez
0 comments posted 20yrs posted by Karel.Deprez

FPT'06 2nd call-for-papers

The 2006 IEEE International Conference on Field-Programmable Technology (ICFPT 06) ------------------------------------...
0 comments posted 20yrs
posted by pinit.kum
0 comments posted 20yrs posted by pinit.kum

Reliability CPLD/FPGA vs Microcontroller

I am doing some research on the reliability of microcontrollers software in comparison to hardware description language...
13 comments posted 20yrs
posted by salewski
13 comments posted 20yrs posted by salewski

XC9500XL Keeper - can it be disabled?

I would like to disable the input signal keeper on a XC9572 CPLD but the inputs still have the keeper even if the "FLOA...
0 comments posted 20yrs
posted by pcw
0 comments posted 20yrs posted by pcw

XILINX 7.1 EDK Solaris 10

Hi, I am just starting to checkout Xilinx 7,1 and its EDK. Running under Solaris 10 I can't launch the GUI, it coredumps...
0 comments posted 20yrs
posted by michael_laajanen
0 comments posted 20yrs posted by michael_laajanen

EDK : FSL macros defined by Xilinx are wrong

Hi everyone, I hope someone @Xilinx will read this. In the new EDK 8.1 the FSL access macros have changed name. And the...
4 comments posted 20yrs
posted by tnt-at-246tNt-dot-com
4 comments posted 20yrs posted by tnt-at-246tNt-dot-com

Xilinx FPGA status after configuration.

Hi all, I am working with a Xilinx Virtex4 and I have troubles with the "after configuration" state of the FPGA. I sear...
2 comments posted 20yrs
posted by sabatini
2 comments posted 20yrs posted by sabatini

XST issues with loop code

All- I had posted before about XST not generating correct netlist for comparisons inside nested loop code within an alw...
1 comments posted 20yrs
posted by jbrower
1 comments posted 20yrs posted by jbrower

Storing Variables into LMB Memory

Hallo, I would store some variables of my software into lmb memory. I have added a section .lmb using "generate linker...
0 comments posted 20yrs
posted by marc
0 comments posted 20yrs posted by marc

clock mux in spartan2e fpga

As I know ,in spartan 2e fpga ,There is no bufgmux,and I want to use clock mux in the design,can some give me some advi...
5 comments posted 20yrs
posted by bjzhangwn
5 comments posted 20yrs posted by bjzhangwn

Is there anything fundamentally wrong with this code?

entity my_entity is port ( clock : in std_logic; reset : in std_logic; input_signal : in std_logic; output_signal : out...
7 comments posted 20yrs
posted by simon.stockton
7 comments posted 20yrs posted by simon.stockton