Our PCB is showing a strange start-up/configuration issue. The board has a virtex4 fpga (xc4vsx35-11) which gives out a DAC-clock, configured as an LVCMOS33, fast slew rate 24 mA output driver.
Now here's the strange thing : when we configure the device through JTAG, the clock is ok. But when we configure it with the SAME bitstream through slave-serial (as will be the case in the endproduct), the clock-output seems to have slowed down significantly : slower rise/fall times, voltage swing not reaching rail-to-rail. Then, when we do a verify through impact it says verify=succesful, and strangely enough after this verify, our clock output is ok again. Note : we use ISE7.1 SP3 on a WinXP machine.
I have checked several scenarios and I am fairly sure this problem has nothing to do with :
- signal integrity
- power levels during startup/config
- DCM lock issues
Does anyone have any clues where I could search next ? I am running out of ideas on this.
Thanks, Bart De Zwaef