Latest threads in Field-Programmable Gate Arrays

Incrmental Compilation in Quartus 5.1

Hello, my co-worker has a very large Altera Quartus 5.1 design that takes about 45 minutes to compile. The project has...

3 20yrs

jjlindula

3 20yrs jjlindula

Xilinx SystemACE : Flash Memory

Does the Flash memory unit connected to the SystemACE SC have to be from AMD? Or can another pin compatible device be u...

0 20yrs

hhu

0 20yrs hhu

Anyone with Xilinx SP305-board ?

Seemed like a good deal, but the board was only around for purchase a few months, so I guess there aren't to many aroun...

31 20yrs

someone

31 20yrs someone

Easily add 4 Gb/s Ethernet link to FPGA systems for control & data transfer

Add 4 Gb/s Ethernet links to FPGA systems easily & at low cost. High bandwidth, low latency control & data transfers. L...

1 20yrs

james.ma

1 20yrs james.ma

LVTTL, LVCMOS or 3.3V-PCI?

what's the difference with LVTTL, LVCMOS and 3.3V-PCI for signalling a PCI fpga/cpld? And if 3.3V-PCI is not available,...

2 20yrs

krbyxtrm

2 20yrs krbyxtrm

ICAP Virtex4 32 bits

Hi out there, does anyone succeeded using ICAP_VIRTEX4 in 32 bit mode? I have implemented a small ICAP controller hangi...

1 20yrs

meres5

1 20yrs meres5

SGMII with Virtex 4 embedded MAC

Hi everyone. I'm trying to implement a gigabit ethernet mac connected to a external gigabit PHY using a SGMII link. I'v...

0 20yrs

SomeOne

0 20yrs SomeOne

Problems with ISE logic optimization

Hello, I'm trying to implement a simple delay line for a 1MHz clock with an even number of inverter cells but the Synth...

6 20yrs

daniel.mosconi

6 20yrs daniel.mosconi

Noise-like Vibration in Measurement Result

Hello, I use Xilinx xcv200e to sum the measurement result in FPGA, in order to average the result in PC. Most of the ti...

0 20yrs

tanceqi

0 20yrs tanceqi

IOBDELAY's delay value

Hi: does anyone know if I set IOBDELAY=BOTH in virtex-II. what's the delay value in the input path? It seems there is n...

7 20yrs

qysheng

7 20yrs qysheng

API on Virtex 4 FPGA or the email of Delon Levi wanted

Hi all, I'm making research on Hardware Evolution and has bought a Development Board named DS-BD-V4LX25LC REVISION 2(VI...

2 20yrs

boxi.yang

2 20yrs boxi.yang

ise8.1 picking local instead of global clk routing?

Hi, I have an old asic prototype that was initially done using ise5.1 and a virtex2, I'm now moving to a virtex4 so I'v...

1 20yrs

langwadt

1 20yrs langwadt

EDK: TCL scripts in pcores directories

Hi EDK experts, I was wondering how are the TCL scripts sitting in each of the pcores/xxxx/data directories supposed to...

1 20yrs

mbmsv

1 20yrs mbmsv

Propagation delay sensitivity to temperature, voltage, and manufacturing

We currently have a Spartan 3 FPGA in our design. In our design, we are using two DCM's specifically. One is driving an...

2 20yrs

folnarh

2 20yrs folnarh

Xlinix ML403 evaluation board

Hello all, First of all I have to say that I'm completely new with the FPGAs. I have just received Xlinx ML403 and I ha...

2 20yrs

misiu75

2 20yrs misiu75

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