2Khz clock signal from 50Hz main frequency with ADPLL

Hello everyone,

I would like to ask if it is possible to generate 2Khz clock signal from 50Hz main frequency using an ADPLL. I have tried SN297 circuit implementation, but couldn't achieve it.

Many thanks in advance,

Rasit

Reply to
raso
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Reply to
Symon

On a sunny day (25 Jul 2006 03:34:12 -0700) it happened "raso" wrote in :

It is important to filter the mains frequency first from spikes and the like. Then perhaps create a pulse at zero crossing to drive the PLL.

Reply to
Jan Panteltje

Dear Jan,

This part is not a problem at all.

What I need to do is to keep the number of 2Khz pulses same as the main 50Hz changes. In perfect condition there are fourty 2Khz cycles within one 50Hz period (20ms/500us). When 50Hz changes (+/- 0.5Hz), 2KHz pulse period should also chance accordingly to stay in lock.

My system clock is 60MHz. I implemented a JK phase detector, a K-counter and a DCO in order to generate 2KHz pulses and this system operates at system clock. The output locks to exact 50Hz very quickly (fed from signal generator), but when I change the reference clock to, lets say, 50.1Hz it starts drifting.

Any help appreciated.

Many thanks, Rasit

Jan Panteltje wrote:

Reply to
raso

On a sunny day (25 Jul 2006 07:45:49 -0700) it happened "raso" wrote in :

You mean per 50 Hz period.

Yes.

Well, I dunno, but I did something like that with 4046 PLL in the 1980ties, divide the 2 kHz to 100 Hz, compare with 100Hz zero crossing derived filtered mains pulses. The issue is the loop filter (lock in range and stability) and loop gain. You need to read up on PLL design perhaps.

All I know :-)

Reply to
Jan Panteltje

raso schrieb:

Sure, otherwise it wouldnt be a PLL. But remember, 0.1 Hz change from 50 Hz is 1/500 = 2 promille = 2000 ppm. Is the pull range of the PLL wide enough? Try changes of +/-50 ppm and see how it works. Than increase the deviation.

Regards Falk

Reply to
Falk Brunner

The 74LS297 has a VERY narrow lock range, compared to traditional analog PLL's. It is generally a fraction of a percent, but I think there is a setting that gives you a couple percent range. It works fine for syncing between a data source running on one xtal clock, from another xtal clock. You would need a digital clock (quartz crystal) that is at some multiple of 50 Hz (not too hard). Then, you'd need a couple of long counter chains to do the divide down.

Are you using an HLL library version of the 74LS297 circuit? If so, where did you get it? I happen to use the real TI chip in one device I built, and a synthesizable version might be good to know about.

Jon

Reply to
Jon Elson

You will also get phase jitter on Mains 50Hz references, as well as the frequency drifts - in most countries they try and keep the number of cycles in a day correct, for operating clocks. So, you need to realise this will always be a historical-fit based lock. What you decide for the next mains cycle might not actually be correct, but you can make a best guess based on the pevious ones.

With MHz to burn, and FPGA, why not use a Freqency Counter/IndexCounter/LoadableDivider, with a slow tracking Up/down coounter on the index. It can be 100% digital, and the tracking speed becomes the PLL-LPF.

Looks like you need to track 1% dF, keeping a nominal 40 clocks / cycle, with a possible divide of 30,000 (!), that should be do-able :)

Many mains systems use zero crossing phase lock, and do not bother about the small freqency variations.

-jg

Reply to
Jim Granville

Hi Jon,

Falk Brunner sent me his VHDL implementation of 74LS297. I modified it so that K-counter and I/D counter (DCO) run at system clock which is

30MHz.

The system has following blocks;

- The first component is an JKFF based phase detector.

- Then, there is a K-counter operating at 30MHz. With 30MHz clock, a full 50Hz period means M=30e6/50=600000 ticks. For minimum jitter, modulus of K counter is set M/2 which is 300000. The borrow pulse decreases the modulus of I/D counter (2KHz DCO) while carry pulse increases it by 1. So in locked condition, it generates 1 carry and 1 borrow pulse within one 50Hz period and they cancel each other.

- I/D counter is a DCO (modulus counter). It operates at 30MHz. When it is locked to 50Hz it has modulus of 15000. When 50Hz changes, the borrow and carry pulses should adjust the modulus of I/D counter (carry pulse increases the modulus by 1, and borrow decreases it by 1). By this way, period of 2kHz pulses is adjusted according to 50Hz input.

- N-Counter which devides 2Khz clock by 40.

The only parameter that I can play with is the modulus of K counter.

I can't use direct implementation of 74LS297. Because, it syncronises f_in and f_out by inserting or deleting 2KHz pulses (I/D pulses). I can't tolerate inserting or deleting 2KHz pulses. It has to keep the number of 2kHz pulses as 40 in each 50Hz period.

Isa

J>

Reply to
raso

Dear Jim,

Could you please explain your idea below?

Many thanks, Isa

Jim Granville wrote:

Reply to
raso

In broad terms:

Table method:

Measure 50Hz (half?) period. appx 50KHz timebase resolves to 0.1% eg gets 20.2ms : Trim and Scale the result, into a lookup table, that then loads the 2KHz divider. ( Suppose you target improve of +/- 1% to +/- 0.1%, that is a ~20 entry table.

Keeping to 0.1%, 2KHz to 0.1% is 2MHz Clock, with ~1000 divider values.

Table/ROM has 20 entries, of 11 bit binary values.

Each new cycle uses the last cycles period, to get a best fit of 40 '2Khz' clocks.

Tracking counter Method : Count the 2KHz clocks you actually get, in a 50Hz period.

For 2KHz, create an 11 bit Divider(from 2MHz), fed from an 11 bit Up/Dn counter. If the Counts_2Khz is ABOVE 40, then Increment the Up/Dn counter, if it is BELOW 40, decrement the Up/Dn counter. ( for higher precision, you might count higher in the divider than 2Khz

- you have not given desired jitter/precision values )

These lock frequecy, or cycles, but do not lock phase.

Most main systems will reset/load the 2KHz on zero cross, to phase lock that. You also want to freqency lock, to have a known phase stepping.

-jg

Reply to
Jim Granville

Jim Granville schrieb:

This is what the 74xx297 is doing with a minimum logic count.

Why so shy? Why not using a "true high speed" clock (like the 30 MHz) to measure the (half)period? Also, 0.1% is not very accurate for a clock (yeah, yeah I know, we have a new result after every cycle).

Sounds very much like 74xx297.

I always wonder how people distinuish between a PLL (PHASE lock) and so called FLL (Frequeny lock). My humble opinion is, that it is nonsense to seperarte phase lock from frequncy lock, since they are mathematical the integral/deviation of each other.

Regards Falk

Reply to
Falk Brunner

Maybe because if your watch runs the same speed as mine, but 10 seconds late, it is in frequency lock, but not phase lock. In 'phase lock' some edge of one signal should be very accurately aligned with some edge of an other.

You can do it both with a 'phase comparator', but there is more to it. Sometimes systems are used that first use a wide bandwidth to lock in [frequency], then switch to (or switch in) a higher gain narrow bandwidth phase loop. This in case mechanical servos for example [for] video head placement. Sometimes multiple stages are used to get ever better precision.

Reply to
panteltje

I don't know all of your requirements, but something I've done before to multiply a slow "clock" like this is to measure each cycle of the slow clock with a much faster reference clock (60MHz in your case) and use the measurement to generate the multiplied clock until the next measurement is available. For your application this would mean measuring each 50Hz (nominally) cycle time in 60MHz ticks (just use a counter). Then divide that measurement result by 40 (easy with shifts and adds) to set the period of your 2kHz clock until the next measurement. The measurement is updated each

50Hz cycle, so the 2kHz clock will always track. The only nasty is that you will have to stretch or shrink the last 2kHz period as the 50Hz period measurement is updated. If you can tolerate this jitter then this is probably the easiest way to generate the locked 2kHz.

A variation of this would be to accumulate several 50Hz period measurements and average them to smooth things out. If you do need a PLL, with a 60MHz clock available you should not have to (or want to) use any analog loop filtering. All digital is the way to go. Or better yet, put the loop filter in software if you have a processor available.

Good luck.

Rob

Reply to
RobJ

raso schrieb:

Wasn't it already this way?

More or less. Wait a tick. Look at the data sheet of the 74xx297, it says the lock range (pull range) of the PLL is

delta_f_max = fc * M / (2*K*N )

using your values

delta_f_max = 50 Hz * 600000 / (2* 300000 * 40) = 1.25 Hz

Hmm, this should be enought.

This is not true. It inserts master clock cycles, in your case, 30 MHz clocks. Which are 1/3000 of a 2 kHz period.

Sure, otherwise you couldnt call it PLL ;-)

Regards Falk

Reply to
Falk Brunner

snipped-for-privacy@yahoo.com schrieb:

Got your point, but I still think the problem (mine?) is the uncertainty in language. Sounds like the common latch/flipflop mixup.

Regards Falk

Reply to
Falk Brunner

It is close, but differs in the phase comparison area. The Freq-table solution is actually frequency locked, and has instant (next cycle) capture time. Something that uses a Phase detector, has a lock time.

Thought: Is the OP using a lock detector, and waiting long enough for the lock to occur ?

For 'normal' clocks, you are right, but this is used to phase decimate (?) mains, which is at the 'crappy' end of the scale in phase/freq, so I chose a simple example point.

Depends if you are an engineer, or a mathematician :)

You can have Frequency lock, and NOT have Phase lock. If you work on the national grid, that subtle difference is vitally important.

A PLL has a lock-time, as it "hunts for lock" - FLLs have a different trade off.

-jg

Reply to
Jim Granville

Jim Granville schrieb:

So has your solution. It's just faster. ;-)

Dunno. My code has none. I gues he uses just a scope to see if the two clocks are in lock. I hope he is triggering on the 50 Hz, not 2 kHz ;-)

As I said before, this sounds like a language problem for me. Even a (fixed) phase relation of other than zero degree is a phase lock.

???

I don't believe in FLLs. The are IMHO "just" PLLs with different jitter properties (filtering, tolerance etc.)

Regards Falk

Reply to
Falk Brunner

A fixed phase relation is a phase offset, not a phase lock (=same angle). The offset may not be moving, but it is not a phase lock.

There have been some spectacular mistakes made, where circuit's were tripped between generators and the national power grids, when the generator WAS frequemcy locked, but NOT with a small enough phase offset ( ie not phase locked, and here phase has magnitude and sign ) - so it is a tad more than a language problem :)

-jg

Reply to
Jim Granville

I/D counter is a 2 divider. In locked condition, its output is 30MHz/2 = 15MHz. Therefore, in addition to N=40 divider, I have to use an f_out prescalar (=7500). In this case :

delta_f_max = fc * M / (2*K*N*f_out_prescalar ) delta_f_max = 50 Hz * 600000 / (2* 300000 * 40 * 7500) = 1.25/7500 Hz

Is this correct?

Isa

Falk Brunner wrote:

Reply to
raso

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