Field-Programmable Gate Arrays

Using XMD for memory dumps (speed)

Hello, I am using the Xilinx XUPV2P board and connect to it using the USB cable. My idea is to upload some data to the...

2 comments posted 20yrs

posted by M.G.v.d.Horst

2 comments posted 20yrs posted by M.G.v.d.Horst

Reinstalled Quartus + Nios II => cygwin1.dll hell :-(

I used to use Cygwin, but when I installed Quartus II and Nios, my local installation stopped working; it couldn't find...

1 comments posted 20yrs

posted by foobar

1 comments posted 20yrs posted by foobar

Problems about the synthesis(XST)

Hi, there We are using a XUP board to implement an algorithm on FPGA right now. Our design is pretty big on the chip. T...

4 comments posted 20yrs

posted by agou.win

4 comments posted 20yrs posted by agou.win

xilinx or altera?

which one should I go in term of easy to learn and use, has more support tool and low cost. they both have web version o...

10 comments posted 20yrs

posted by jetq5188

10 comments posted 20yrs posted by jetq5188

Re: Quartus and source control (continued)

I'm starting a new thread on this since Google locked me out from replying. Regarding conflicts using CVS, use SVN and...

11 comments posted 20yrs

posted by geomills

11 comments posted 20yrs posted by geomills

S3 starter kit, command-line

Any idea why flash programming would fail on the old starter kit (S3, not S3E)? I cant even load the Digilent demo bitf...

7 comments posted 20yrs

posted by burn.sir

7 comments posted 20yrs posted by burn.sir

Is necessary to use Modsim on DDR Memory development?

Dear everyone We are doing DDR interface design with the Xilinx Virtex-4. Actually, it's kind of straight forward, I ju...

2 comments posted 20yrs

posted by ssc3k

2 comments posted 20yrs posted by ssc3k

Power Supply Sequencing to V4 MGTs

Does anyone know if it's a problem if the LDO supplies to V4 MGTs come up before supplies to the rest of the chip (i.e....

3 comments posted 20yrs

posted by petermendham

3 comments posted 20yrs posted by petermendham

Open-source JTAG software?

Does anyone know of any open-source software which will program an XCF04S (Xilinx serial PROM) on JTAG? It also needs to...

16 comments posted 20yrs

posted by eml

16 comments posted 20yrs posted by eml

Ultracontroller II: PROM solution in EDK 8.1

Has anyone tried Ultracontroller PROM solution of V4 in EDK 8.1i? The reference example is built by EDK 7.1i. I went th...

3 comments posted 20yrs

posted by louis99.lin

3 comments posted 20yrs posted by louis99.lin

Xilinx PowerPC run Program out of SDRAM

Hi everyone, I have a Problem that's equal to that discussed in January this year (PPC Memory Management, 27. January 2...

3 comments posted 20yrs

posted by peter.kampmann

3 comments posted 20yrs posted by peter.kampmann

FPGA Memory Power

All, A general (and possibly very naive!?) question: for data intensive routines (for example functions within image or...

5 comments posted 20yrs

posted by daniel.larkin

5 comments posted 20yrs posted by daniel.larkin

Simple state machine in CUPAL

I'm working on a Power-On-Jump GAL/SPLD for an 8080 machine. I'm trying to figure out how to write it using Sequence/Pr...

7 comments posted 20yrs

posted by grant

7 comments posted 20yrs posted by grant

High rate data transfer from off-chip mem to FSL co-proc...

Hi guys, Sorry this subject was discussed in a different way a year ago. However: I have a Microblaze based system and...

2 comments posted 20yrs

posted by amirhossein.gholamipour

2 comments posted 20yrs posted by amirhossein.gholamipour

Reset asynchronous assertion synchronous deassertion

Hi Eveyone, The specifications goes something like this : The device core asserts reset to the device peripherals async...

4 comments posted 20yrs

posted by arant.agrawal

4 comments posted 20yrs posted by arant.agrawal