All,
A general (and possibly very naive!?) question: for data intensive routines (for example functions within image or video processing algorithms) power consumption is apparently dominated by the memory rather than than the datapath logic (or at least memory power is as important). Whilst this seems reasonable if there is off-chip memory accesses so theres considerable power lost in the decode logic, routing, possible access arbitration, etc,etc). I'm not clear why this would be the case for on-chip sram since the routing would seem to be minimal and less control logic would be necessary for tiny SRAM memory relative to off-chip SDRAM for example?. Is it because that everytime a memory location is accessed, its not just the switching in the transistors at this memory location thats consuming power, but rather a full row/column etc?
As a "hard" example lets say you have 2 single port SRAMs containing
256 8-bit words and the data path consists of adding together a value from each SRAM every clock cycle. Will power consumption in the memories dominate in such a scenario? and why?I'd be delighted if anyone could elaborate on this or indeed point me to some decent links on the topic
thanks Daniel