Xilinx 2 DCMs with delay on lock

Hio folks,

I'm trying to find a document that describes adding a delay between the inverted lock signal of one DCM that feeds forward to the reset of the next DCM.

I have seen this document before, so I know it exists. Anyone know where I can find this doc?

Brad Smallridge aivision

Reply to
Brad Smallridge
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Brad, I believe it is in the old app notes describing the DLLs in Virtex.

Reply to
Ray Andraka

I think the following refers to the situation you have described -

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HTH.

Reply to
VC

Yes. Thank you VC. Those did help.

Brad Smallridge aivision

Reply to
Brad Smallridge

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