Field-Programmable Gate Arrays

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IE7 and ISE Help

Why doesn't the particular Help page display in IE7 when a Help button is clicked on in ISE? TIA. Rog.
0 comments posted 19yrs
posted by enquiries
0 comments posted 19yrs posted by enquiries

Double buffering

I've read much about Double Buffering, especially that it is good practice (on Xilinx devices) to double buffer data si...
3 comments posted 19yrs
posted by davidhughes330
3 comments posted 19yrs posted by davidhughes330

logic analyzer using FPGA

Hi. Is there any ready open source (or not so open) logic analyzers based on FPGA + (S|D)RAM? I mean, we need to connec...
2 comments posted 19yrs
posted by hypermodest
2 comments posted 19yrs posted by hypermodest

run a counter without a clock

Hi to everyone, I'm trying to generate a 5-10 ns pulse width out of an edge, without the use of any clock, just with in...
17 comments posted 19yrs
posted by alessandro.basili
17 comments posted 19yrs posted by alessandro.basili

MPMC2 DDR2 simulation

hi I think I am close to get it fully working, but some things are still messy MPMC2 has only verilog but EDK simulatio...
1 comments posted 19yrs
posted by Antti.Lukats
1 comments posted 19yrs posted by Antti.Lukats

Verilog problem: default case to set signal xxxx

Hi all, I always found people like to add default branch like below: case(branch) ... ... [all the possible branch] ......
11 comments posted 19yrs
posted by zhushenli
11 comments posted 19yrs posted by zhushenli

MicroBlaze & top module?

Hello, I have defined some signals which I plan to change dinamicaly with MicroBlaze as submodule. Signals are organize...
0 comments posted 19yrs
posted by krassi
0 comments posted 19yrs posted by krassi

Altera MAX3000A OE and GCLR-Pins

Is it essential to connect the unused OE and GCLR-Pins of an Altera MAX3000A to ground??? the Quartus Pin-file shows GN...
2 comments posted 19yrs
posted by manfred.balik
2 comments posted 19yrs posted by manfred.balik

jtag loader for picoblaze

hi all we have implemented a picoblaze in vertex 4 kit and we r in the path of implementing JTAG loader to reconfigure...
3 comments posted 19yrs
posted by umeshmgowda
3 comments posted 19yrs posted by umeshmgowda

types of FPGA

What are types of FPGA like antifuse ,sram based.what is difference under what category cyclone cyclone II device fall t...
1 comments posted 19yrs
posted by vsrpkumar
1 comments posted 19yrs posted by vsrpkumar

Are FPGAs available with ADCs onchip ?

Hi, Could anybody tell me whether any manufacturer of FPGAs provide onchip ADC ? Regards jay
2 comments posted 19yrs
posted by jaycp.iitkgp
2 comments posted 19yrs posted by jaycp.iitkgp

What's Nonpipelined bus mean?

Hi all, I always heard Nonpipelined bus. Is any bus Nonpipelined? Or is there Pipelined bus or other types of bus. Thank...
6 comments posted 19yrs
posted by zhushenli
6 comments posted 19yrs posted by zhushenli

Xilinx EDK Problem

Hi I have a design with a Power PC that I am trying to put through ISE. Th problem I have is that I get the following e...
1 comments posted 19yrs
posted by maxascent
1 comments posted 19yrs posted by maxascent