In order to start working with USB 2.0 data transfers, I used two boards for implementation and cross verification. The boards are:
- Cy 3618 development board for FX2LP chips which support USB 2.0 transfers
- FPGA developement kit which houses Cy7C68013A chip with all the connections to the FPGA. (By all connections I mean the ones which matter, as we will see later in the post)
You will also require "Ez-Usb Control Panel" application from Cypress as well as "Ez Usb development kit" which after installation will create a "Cypress\usb\" folder in the root directory, if you install in the default location. The important folders are:
A.1. Cypress\usb\Drivers which contain a generic driver in the root named ezusbw2k.inf A.2. Cypress\usb\Target\Lib\LP folder which contain Ezusb.lib and USBJmpTb.a51 to be used while programming with Keil tools (if you have FX2 or EzUSB development board, then use the respective folders, I am using FX2LP so I am using LP folder). A.3. Cypress\usb\Target\Inc which includes fx2.h, fx2regs.h, syncdly.h for FX2 based boards, otherwise there are ezregs.h, ezusb.h for the development board and kit. A.4. Cypress\usb\Examples which contain respective examples for FX2/FX2LP/EzUSB/FX1/SX2 chips, whichever are applicable in your case.
Since I had the facility of development board (EzUSB) I first worked on it to get the board working and loading the hex file (or programming the FX2LP chip on the EzUSB developement board) using both the Keil debugger and the EzUSB Control Panel. I followed the following steps and got the same working responce for identical hex file using both Keil downloading and EzUSB Control Panel:
- Select no EEPROM on the board by bringing the toggle switch (SW2) down.
- Plug in the USB device.
- Open "Windows Control Panel" and from there Systems/hardware/device manager. Check to see if after connecting your board, the "Universal Serial Bus controllers" heading contains "Cypress EzUSB FX2 (68613) - EEPROM Missing" field. If it doesnt and its the first time, the system has started on your computer, then you need to load the driver as explained in bullet A.1.
- Run EzUSB Control Panel.
- Open Page 10 of "Ez USB contents and tutorial" which is accessible from the help menu of Ez USB Control Panel and follow instructions until the end of page 13.
- After successful tutorial completion, disconnect device and close control panel.
- Select EEPROM Enable on the Ez USB development board (SW2 in upward position), also make sure that the SW1 named "EEPROM Select" is indicating small EEPROM option.
- Re-Connect the USB cable or device and check from device manager that now it should automatically load the driver but this time its stating "Ez-USB advanced Development Board FX2LP(Keil Monitor)".
- A green LED should turn on the board (D7) indicating the monitor has been uploaded on to the FX2 chip.
- Continue following the tutorial "Ez-USB contents and tutorial" from page 14 onwards until you reach page 19.
By now you will have established the following:
- Any hex file provided by the vendor or generated can be downloaded onto FX2 chip using Ez USB control Panel
- The same hex file can be used for monitoring and debugging the application by using Keil Monitor.
An EzUSB chip connected with the FPGA is in the same situation of "Cypress EzUSB FX2 (68613) - EEPROM Missing".
Hence, if you write some code and generate the hex file you can download it onto FX2 chip of the FPGA board using EzUSB Control Panel.
Then you can program the FPGA with bit file and you will successfully interface the two.
There is one small catch, you have to make sure that the FGPA is not resetting the USB which is active low (or depends upon your hardware, you have to check the schematic). So whatever your code in your FPGA, it must always include the reset pin pulled high to ensure that the FPGA doesnt reset your FX2 chip.
By default the FX2 chip has CLKOUT pin enabled and it is running at 12 MHz. The first experiment could be to interface the CLKOUT pin, bring it to FPGA and output the same on a general purpose header to be confirmed with an oscilloscope.
When you see the 12MHz pulse, x. you will reset the FPGA, y. reporgram the FX2 chip with a difference setting of CPUCS = 0x12 or0x0A for 48MHz/24MHz respectively, z. download the bit file onto FPGA again, and see the outputs there.
If you can, then your FPGA is not resetting the FX2 and your keil hex file generation and hex file downloading will be established.
So now, you can write FX2 specific codes for addressing USB modes and endpoints etc. and write a master/slave FIFO or GPIF compatible interface on the FPGA for data communication.
We will get to that in a while...
I hope it helps...