Field-Programmable Gate Arrays

Prefetch buffer in microblaze

Hi guys, Does the instruction prefetch buffer in microblaze block if the required (prefetch) instruction takes more tha...

1 comments posted 19yrs

posted by vmurali

1 comments posted 19yrs posted by vmurali

Old XCell journals gone?

Looks like Xilinx has pulled the old XCell journals off the website. Someone was asking about my article on downconvert...

5 comments posted 19yrs

posted by ray

5 comments posted 19yrs posted by ray

SPI Flash on Avnet Spartan 3E Eval Kit

Hi, Any good ideas for how to program the the SPI Flash on the Avnet Spartan 3E Evaluation Kit? The Avnet instructions...

5 comments posted 19yrs

posted by wburris

5 comments posted 19yrs posted by wburris

Spartan-3E or Generic FPGA -> PC133 interface details??

Hi, recently I've started using FPGAs for all sorts of things, and currently I'm working on a couple designs that would...

2 comments posted 19yrs

posted by slax0r.hax0r

2 comments posted 19yrs posted by slax0r.hax0r

ISE on a cluster?

Hi, Is it possible to run Xilinx ISE on a cluster? In the office there are about 20 desktops, all networked & idle, and...

4 comments posted 19yrs

posted by jetmarc

4 comments posted 19yrs posted by jetmarc

Stratix II GX Transceivers

Hello, I'm looking to do a design involving data rates near 4Gbps and was looking at using Altera's Stratix II GX trans...

3 comments posted 19yrs

posted by jjlindula

3 comments posted 19yrs posted by jjlindula

modular design / PlanAhead

Hi, Does anyone have experience with modular design flow or PlanAhead? Could you answer my questions related to it: 1)...

1 comments posted 19yrs

posted by wojtek2u

1 comments posted 19yrs posted by wojtek2u

FPGA application field

Hello everybody. It seems, I wish to build my career as engineer who use FPGA to construct ad hoc designs, in the field...

14 comments posted 19yrs

posted by tenteric

14 comments posted 19yrs posted by tenteric

XC3020-50 board documentation

Hi all, Would anyone be able to direct me to (or provide me with) any materials related to this board that I've got. ht...

4 comments posted 19yrs

posted by sjb

4 comments posted 19yrs posted by sjb

FPGA workstation - should I wait for Window Vista?

Hi all, I wonder if anyone here are in the same situation as me. I am think of buying a new PC, but wondering if I shou...

15 comments posted 19yrs

posted by joseph.yiu

15 comments posted 19yrs posted by joseph.yiu

Bus Lock

Hi all, I'm working with an virtex2pro and EDK. I need help on locking bus for sequential writing on a register. I woul...

0 comments posted 19yrs

posted by luca.cenzato

0 comments posted 19yrs posted by luca.cenzato

DVI clock generation

Hi! I am starting a DVI Board design. The purpose is to generate DVI data in an FPGA. interface it to an DVI transmitte...

9 comments posted 19yrs

posted by thehansman

9 comments posted 19yrs posted by thehansman

Hardware in the loop simulation for Altera design

Hi, I am presently involved in a project dealing with a pretty large design in a Stratix II GX chip with a Nios II proc...

4 comments posted 19yrs

posted by jean-francois.hasson

4 comments posted 19yrs posted by jean-francois.hasson

Xilinx XST Incremental Design Change

I have a bug and it seems to manifest itself only in stealth mode. When I move my LEDs to see what the trouble is, the...

2 comments posted 19yrs

posted by bradsmallridge

2 comments posted 19yrs posted by bradsmallridge

So who has used Lattice FPGAs recently?

One of my vendors (reps, really) has expressed a desire to sell me Lattice devices based on low standby power, low cost...

10 comments posted 19yrs

posted by peter.smith8380

10 comments posted 19yrs posted by peter.smith8380