Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

So who has used Lattice FPGAs recently?

One of my vendors (reps, really) has expressed a desire to sell me Lattice devices based on low standby power, low cost...
10 comments posted 19yrs
posted by peter.smith8380
10 comments posted 19yrs posted by peter.smith8380

ModelSim Xilinx edition new bug?

Xilinx ISE 8.2i service pack 3 ModelSim XE III 6.1e VHDL system When I build a block ram using CoreGen in Xilinx ISE it...
2 comments posted 19yrs
posted by danielgkNOSPAM
2 comments posted 19yrs posted by danielgkNOSPAM

Spartan3 Configuration Puzzler

Hi, I'm using a microcontroller to configure a Spartan-3 device. The device seems to configure ok (the design works as...
13 comments posted 19yrs
posted by dave.bryan
13 comments posted 19yrs posted by dave.bryan

pre-synthezis simulation in ModelSim for Actel

I'm using Model for Actel. When performing pre-synthesis simulation in ModelSim, I observe 'unknown' signals in design....
4 comments posted 19yrs
posted by karollo
4 comments posted 19yrs posted by karollo

Xilinx ML555 availability

Hi folks, Does anyone knows when will the ML555 (LXT/8x PCIe) board be officially released (and available for ordering ?...
1 comments posted 19yrs
posted by sderrienREMOVE
1 comments posted 19yrs posted by sderrienREMOVE

verilog 2 VHDL translator

Hi all, I'm looking for a verilog to VHDL translator. Does anybody can point me for a free tool please? thanks in advanc...
3 comments posted 19yrs
posted by francesco_poderico
3 comments posted 19yrs posted by francesco_poderico

Bus structures question (Spartan 3)

hi, currently I am working on a small hobby project with the Spartan 3 Starter Kit board from Xilinx. I use ISE WebPack...
8 comments posted 19yrs
posted by jboehm
8 comments posted 19yrs posted by jboehm

Xilinx FIFOs round 2 - BUG-BUG in MPMC2

it seems that Xilinx has real problems getting even simple FIFOs to work after having problems with Virtex4 coregen FIF...
5 comments posted 19yrs
posted by Antti.Lukats
5 comments posted 19yrs posted by Antti.Lukats

Digital PLL and FM demodulation

Hello, PLL is a good way to do FM demodulation in analogue domain. What about its use in digital domain? Why not to use...
4 comments posted 19yrs
posted by ma
4 comments posted 19yrs posted by ma

problems with verilog SDRAM models

I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM that I want to be able to control via an FPGA o...
9 comments posted 19yrs
posted by wallge
9 comments posted 19yrs posted by wallge

opb master kills linux?

I have a xilinx v4 project running mv linux 2.6.10. I have a custom peripheral I made that includes DMA on the opb bus...
2 comments posted 19yrs
posted by someone
2 comments posted 19yrs posted by someone

nios2 toolchain sources

EHLO (o; What happened to the nios2 sources which were once accessable via the doc/degree ftp login documented on the A...
9 comments posted 19yrs
posted by me
9 comments posted 19yrs posted by me